Conference Paper

Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
DOI: 10.1109/IEDM.2003.1269290 Conference: Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Source: IEEE Xplore

ABSTRACT Dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated on low EOT single layer HfO2 and stacked HfO2/SiO2 gate dielectrics. It was found that the work function values of metal gates on HfO2 and on SiO2 are similar. Thermal anneal studies of selected metals on the above dielectrics were also performed to evaluate the change in EOT and VFB values.

  • [Show abstract] [Hide abstract]
    ABSTRACT: Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with L<sub>M1</sub>/ L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO<sub>2</sub>) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and f<sub>T</sub>-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having L<sub>M1</sub>/L ratio as 1/2, proving to be the best choice among various L<sub>M1</sub>/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better f<sub>T</sub>-gain relationship.
    IEEE Transactions on Electron Devices 02/2008; · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping ( NA ), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.
    IEEE Transactions on Electron Devices 11/2008; · 2.06 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a two-dimensional (2D) analytical sub-threshold model for a novel sub-50 nm multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain-induced barrier lowering, sub-threshold drain current and sub-threshold swing. Results reveal that MLGEWE-RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high-speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.
    International Journal of Numerical Modelling Electronic Networks Devices and Fields 10/2008; 22(3):259 - 278. · 0.54 Impact Factor


Available from