Conference Paper
Compatibility of dual metal gate electrodes with highk dielectrics for CMOS
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
DOI: 10.1109/IEDM.2003.1269290 Conference: Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International Source: IEEE Xplore

Article: LinearityDistortion Analysis of GMETRC MOSFET for High Performance and Wireless Applications
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ABSTRACT: In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multilayered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: , , , and figureofmerit (FOM) metrics; , , IIP3 and 1dB compression point, has been obtained. It is shown that, the incorporation of multilayered architecture on gate material engineered trapezoidal recessed channel (GMETRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for lownoise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth () or negative junction depth (NJD) have been examined for GMETRC MOSFET and compared its effectiveness with MLGMETRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.Journal of Semiconductor Technology and Science 01/2011; 11(3). · 0.58 Impact Factor  [Show abstract] [Hide abstract]
ABSTRACT: In this paper, a twodimensional (2D) analytical subthreshold model for a novel sub50 nm multilayeredgate electrode workfunction engineered recessed channel (MLGEWERC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO2based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, draininduced barrier lowering, subthreshold drain current and subthreshold swing. Results reveal that MLGEWERC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for highspeed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.International Journal of Numerical Modelling Electronic Networks Devices and Fields 10/2008; 22(3):259  278. · 0.54 Impact Factor 
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