Source/drain engineering for sub 100-nm technology node
ABSTRACT ITRS2001 indicates 25-nm physical gate length and 10-17-nm extension depth are required in 65-nm technology node for high performance application. It means resultant requirement of precisely controlled conventional process and new material and process introduction. Though ion implantation and spike RTA are still base line technology for doping, it should be carefully optimized in process integration avoiding implantation-induced damage and transient enhanced diffusion. Careless process sequence might cause undesired enlargement of junction depth even in LPCVD temperature annealing. Sidewall scaling is also necessary to reduce source and drain parasitic resistance and it relates to the contact junctions and silicidation process. Cobalt salicide is widely used in recent technology node. However, its silicon consumption in silicidation process requires relatively deep contact junctions and tends to cause the interference of the contact junction to the channel region. Therefore, lower silicon consumption silicide material such as nickel SALICIDE is one of the solutions. NiSi silicidation can be performed at low temperature and silicon consumption is about 80% of CoSi2 silicide under the same silicide thickness condition. Additionally, more structural approach like elevated source/drain using selective silicon or silicon-germanium will be introduced to solve severer constraints.
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ABSTRACT: A new technique in qualification of low temperature nickel silicide process is studied. Bare silicon wafers are first oxidized to form a thick film of thermal oxide, followed by nickel and titanium film stack deposition. The samples are then annealed at low temperature using a rapid thermal processing tool. It is shown that the nickel and titanium film stack forms an alloy above the thermal oxide layer. This alloy's sheet resistance depends on the nickel/titanium film thickness, nickel to titanium thickness ratio, annealing temperature and time. Using the high temperature sensitivity compared to that in conventional technique, this new technique offers an accurate, reliable, and cost effective approach for process qualification, rapid thermal annealing chamber matching and daily monitoring.01/2011;
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ABSTRACT: In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.IEEE Transactions on Electron Devices 03/2011; · 2.06 Impact Factor