A CMOS multi-channel 10Gb/s transceiver
Fujitsu Labs. Ltd., Kawasaki, JapanDOI: 10.1109/ISSCC.2003.1234212 Conference: Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Source: IEEE Xplore
A quad 10Gb/s transceiver in 0.11μm CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.
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ABSTRACT: This paper presents a 10 Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47 μm×85 μm and 13.2 mW for the equalizer and 145 μm×80 μm and 10 mW for the ISI monitor.VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
Conference Paper: An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling[Show abstract] [Hide abstract]
ABSTRACT: This paper presents a 4-PAM adaptive decision-feedback equalizer (DFE) for chip-to-chip signaling. The DFE adapts to the channel impulse response by observing a calibration sequence sent across the channel. Uninterrupted signaling is maintained across a parallel bus by providing an additional channel and using multiplexors to reroute the signals of the channel being calibrated. Using the intermittent calibration sequence instead of the conventional LMS adaptation technique removes the need to generate an error signal, eliminating the associated analog blocks. Also presented is a novel method of using the DFE adaptation circuits to extract the system's pulse response. The complete transceiver is implemented in a 0.18 μm CMOS process.SOC Conference, 2004. Proceedings. IEEE International; 10/2004
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ABSTRACT: This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-μm CMOS technology the module has a size of 0.25×1.4 mm<sup>2</sup>. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2<sup>23</sup>-1 and a bit-error rate threshold of 10<sup>-12</sup>. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.IEEE Journal of Solid-State Circuits 04/2005; 40(3-40):736 - 743. DOI:10.1109/JSSC.2005.843624 · 3.01 Impact Factor
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