Conference Paper

A CMOS multi-channel 10Gb/s transceiver

Fujitsu Labs. Ltd., Kawasaki, Japan
DOI: 10.1109/ISSCC.2003.1234212 Conference: Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Source: IEEE Xplore

ABSTRACT A quad 10Gb/s transceiver in 0.11μm CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.

  • [Show abstract] [Hide abstract]
    ABSTRACT: A 20Gb/s simultaneous bidirectional transceiver uses a resistor-transconductor hybrid in a standard 0.11 mum CMOS process. The 7mW hybrid works in a continuous-time domain without any replica driver and eliminates the need for the precise matching between the replica- and main-driver characteristics
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
  • [Show abstract] [Hide abstract]
    ABSTRACT: A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 m CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW.
    IET Circuits Devices & Systems 11/2008; 2(5-2):409 - 421. DOI:10.1049/iet-cds:20080111 · 0.91 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3” FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor inter-symbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5$\,\times$ energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation.
    IEEE Journal of Solid-State Circuits 01/2012; 47(4):926-937. DOI:10.1109/JSSC.2012.2185370 · 3.11 Impact Factor