Radiation test methodology for SRAM-based FPGAs by using THESIC+
ABSTRACT Benefits resulting from the adoption of SRAM-based FPGAs as design target technology in space applications are manifold. These devices, however, exhibit a potentially high susceptibility to single event upsets (SEU) due to the presence of a large number of configuration memory cells. As fault injection alone is not able to reach every circuitry inside FPGA, radiation ground testing is mandatory in order to perform the analysis on a larger set of SEU upsets. This paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system.
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ABSTRACT: This paper presents a survey of CMF (common-mode failures) in redundant systems with emphasis on VLSI (very large scale integration) systems. The paper discusses CMF in redundant systems, their possible causes, and techniques to analyze reliability of redundant systems in the presence of CMF. Current practice and results on the use of design diversity techniques for CMF are reviewed. By revisiting the CMF problem in the context of VLSI systems, this paper augments earlier surveys on CMF in nuclear and power-supply systems. The need for quantifiable metrics and effective models for CMF in VLSI systems is re-emphasized. These metrics and models are extremely useful in designing reliable systems. For example, using these metrics and models, system designers and synthesis tools can incorporate diversity in redundant systems to maximize protection against CMFIEEE Transactions on Reliability 10/2000; · 2.29 Impact Factor
Conference Proceeding: Novel fault-tolerant adder design for FPGA-based systems[show abstract] [hide abstract]
ABSTRACT: Proposes a novel fault-tolerant adder which is suitable for highly dependable systems implemented by means of field-programmable gate arrays (FPGAs). Compared to alternate conventional designs, the one presented here allows one to achieve fault-tolerance at lower design costs. A prototype has been developed, whose expected behavior has been verified by means of post-layout simulations and experimental measurements. Although our adder has been conceived for FPGA-based systems, it is also suitable to be implemented by means of VLSI and very deep sub-micron technologiesOn-Line Testing Workshop, 2001. Proceedings. Seventh International; 02/2001