Radiation test methodology for SRAM-based FPGAs by using THESIC+
INO - Istituto Nazionale di Ottica, Florens, Tuscany, Italy
DOI: 10.1109/OLT.2003.1214388 Conference: On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Benefits resulting from the adoption of SRAM-based FPGAs as design target technology in space applications are manifold. These devices, however, exhibit a potentially high susceptibility to single event upsets (SEU) due to the presence of a large number of configuration memory cells. As fault injection alone is not able to reach every circuitry inside FPGA, radiation ground testing is mandatory in order to perform the analysis on a larger set of SEU upsets. This paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system.
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