Conference Paper

Radiation test methodology for SRAM-based FPGAs by using THESIC+

INO - Istituto Nazionale di Ottica, Florens, Tuscany, Italy
DOI: 10.1109/OLT.2003.1214388 Conference: On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Source: IEEE Xplore

ABSTRACT Benefits resulting from the adoption of SRAM-based FPGAs as design target technology in space applications are manifold. These devices, however, exhibit a potentially high susceptibility to single event upsets (SEU) due to the presence of a large number of configuration memory cells. As fault injection alone is not able to reach every circuitry inside FPGA, radiation ground testing is mandatory in order to perform the analysis on a larger set of SEU upsets. This paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system.

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    • "The effects induced by SEUs on RAM-based FPGAs have been investigated recently through radiation experiments [4]–[6], where the predominant effect that was observed was the SEFI. More recently, an analysis that combines the results of radiation testing with those obtained while analyzing the meaning of every bit in the FPGAs configuration memory was reported in [7], [8]. "
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    ABSTRACT: Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.
    IEEE Transactions on Nuclear Science 11/2005; DOI:10.1109/TNS.2005.856543 · 1.46 Impact Factor
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    ABSTRACT: Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new fault injection environment, which offers an alternative to radiation testing for evaluating the effects of charged particles on the configuration memory of SRAM-based FPGA devices. This paper describes the fault injection environment and reports preliminary results gathered on some benchmark circuits.
    12/2001: pages 101-116;
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