Conference Paper
A 2.5V CMOS wideband sigmadelta modulator
Instituto de Microelectronica de Sevilla;
DOI: 10.1109/IMTC.2003.1208156 Conference: Instrumentation and Measurement Technology Conference, 2003. IMTC '03. Proceedings of the 20th IEEE, Volume: 1 Source: IEEE Xplore
 Citations (7)
 Cited In (0)

Article: 14bit 2.2MS/s sigmadelta ADC's
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ABSTRACT: This paper presents the design and test results of a fourthorder and sixthorder 14bit 2.2MS/s sigmadelta analogtodigital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS doublepoly triplelevel metal 3.3V process. The design objective for these ADC's was to achieve 85 dB signaltonoise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigmadelta topology. The fourthorder modulator consists of two cascaded secondorder stages which include 1bit and 5bit quantizers, respectively. The sixthorder modulator has a 222 cascade structure and 1bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gainmatching requirements between the analog and digital sectionsIEEE Journal of SolidState Circuits 08/2000; · 3.06 Impact Factor  [Show abstract] [Hide abstract]
ABSTRACT: Oversampled sigmadelta (EA) modulators offer numerous advantages for the realization of highresolution analogtodigital (A/D) converters. This paper explores how oversampling and feedback can be employed in highresolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 221 cascaded multibit architecture suitable for operation from a 2.5V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress inband digitaltoanalog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5μm doublepoly triplemetal CMOS technology. Fully differential doublesampled switchedcapacitor integrators enable the modulator to achieve 95dB dynamic range at a 4Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5V supplyIEEE Journal of SolidState Circuits 01/2002; · 3.06 Impact Factor  [Show abstract] [Hide abstract]
ABSTRACT: The design of a highresolution, highspeed, deltasigma analog todigital converter that operates from a single 3.3V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switchedcapacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 211 cascade topology with optimized coefficients. For an oversamplingratio of only 24, the converter achieves a signaltonoise ratio of 87 dB, a signalto(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5μm CMOS technology, in a 5mm<sup>2</sup> die area, and consumes 200 mW from a 3.3V power supplyIEEE Journal of SolidState Circuits 08/1999; · 3.06 Impact Factor
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