Conference Paper

A novel 64-point FF/IFFT processor for IEEE 802.11(a) standard

IHP, Frankfurt, Germany
DOI: 10.1109/ICASSP.2003.1202359 Conference: Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on, Volume: 2
Source: IEEE Xplore

ABSTRACT A novel 64-point FFT/IFFT processor is presented in this article, named TURB064, developed primarily for the application for the IEEE 802.11 (a) standard. The processor does not use any digital multiplier or RAM. It has been fabricated and tested successfully. Its core area is 6.8 mm2 and the average power consumption is 41 mW at 1.8 V @ 20 MHz frequency. Compared to some other existing IP cores and ASIC chips TURB064 needs a smaller number of clock cycles and consumes less power.

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Available from: Ulrich A. Jagdhold, Nov 20, 2014
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    ABSTRACT: Cottbus, Techn. University, Diss., 2004 (Nicht für den Austausch).
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    ABSTRACT: In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-μm BiCMOS technology. The core area of this chip is 6.8 mm<sup>2</sup>. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.
    IEEE Journal of Solid-State Circuits 04/2004; 39(3-39):484 - 493. DOI:10.1109/JSSC.2003.822776 · 3.01 Impact Factor
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    ABSTRACT: In this paper, we introduce a fixed-point 16-bit 64 point FFT processor architecture for OFDM-based wireless applications. The processor is based on the DIT (decimation-in-time) radix-2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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