Conference Paper
A novel 64point FF/IFFT processor for IEEE 802.11(a) standard
IHP, Frankfurt, Germany
DOI: 10.1109/ICASSP.2003.1202359 Conference: Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on, Volume: 2 Source: IEEE Xplore

Conference Paper: An Efficient 64point Pipelined FFT Engine
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ABSTRACT: The Fast Fourier Transform (FFT) is a very important algorithm in signal processing, software defined radio and the most promising modulation technique i.e. Orthogonal Frequency Division Multiplexing (OFDM). This paper describes the design and implementation of a fully pipelined 64point FFT engine in programmable logic. The FFT takes 16bit fixed point complex numbers as input and after a known pipelined latency of 20 clock cycles produces the desired output. The input data samples are fed in parallel to the FFT engine to generate outputs in parallel. The architecture is capable of performing FFT operation without changing the internal coefficients which makes it highly suitable for practical applications. The architecture requires 25% multiplication operations compared to conventional CooleyTukey approach. Hence it leads to low power and area saving.Advances in Recent Technologies in Communication and Computing (ARTCom), 2010 International Conference on; 11/2010 
Conference Paper: VLSI implementation of fast Fourier transformation for OFDMbased highspeed wireless applications
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ABSTRACT: In this paper, we introduce a fixedpoint 16bit 64 point FFT processor architecture for OFDMbased wireless applications. The processor is based on the DIT (decimationintime) radix2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDMbased highspeed wireless applications.SolidState and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004  [Show abstract] [Hide abstract]
ABSTRACT: In this paper, we present a novel fixedpoint 16bit wordwidth 64point FFT/IFFT processor developed primarily for the application in an OFDMbased IEEE 802.11a wireless LAN baseband processor. The 64point FFT is realized by decomposing it into a twodimensional structure of 8point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix2 64point FFT algorithm. The complex multiplication operations are realized using shiftandadd operations. Thus, the processor does not use a twoinput digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64point FFT/IFFT processor has been fabricated and tested successfully using our inhouse 0.25μm BiCMOS technology. The core area of this chip is 6.8 mm<sup>2</sup>. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one paralleltoparallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.IEEE Journal of SolidState Circuits 04/2004; · 3.06 Impact Factor
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