Conference Paper

A methodology for accurate modeling of energy dissipation in array structures

Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
DOI: 10.1109/ICVD.2003.1183157 Conference: VLSI Design, 2003. Proceedings. 16th International Conference on
Source: DBLP

ABSTRACT There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system level energy consumption. In this paper, we propose a new methodology to develop analytical models for accurately estimating energy dissipation in array structures. The methodology is based on the characterization of arrays for energy as a function of micro-architecture level inputs. The coefficients of the function are extracted using circuit level simulations. We apply the proposed methodology to develop energy models for three different array structures used in the Motorola e500 processor core. The models are validated by comparing them against post-layout SPICE simulation. The energy models are seen to be highly accurate with an error margin of less than 8%. While the experiments are specific to the e500 processor core based array structures, the methodology is generic and can be used to develop energy models for array structures of any SOC design.

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    ABSTRACT: While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the Implementation Dependent Array Power (IDAP) estimator, that model power dissipation in SRAM based arrays accurately based on a high-level description of the array, parameterized by the array operations, the implementation styles, and various technology dependent parameters. The methodology is generic and the IDAP tool has been validated on industrial designs across a wide variety of array implementations in the e500 processor core. For these industrial designs, IDAP generates high-level estimates for dynamic power dissipation that are highly accurate with an error margin of less than 22.2% of detailed (layout extracted) SPICE simulations.
    2003 International Conference on Computer-Aided Design (ICCAD'03), November 9-13, 2003, San Jose, CA, USA; 01/2003
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    [Show abstract] [Hide abstract]
    ABSTRACT: While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the implementation-dependent array power (IDAP) estimator, that model power dissipation in SRAM-based arrays accurately based on a high-level description of the array. The models are parameterized by the array operations and various technology dependent parameters. The methodology is generic and the IDAP tool has been validated on industrial designs across a wide variety of array implementations in the e500 processor core (e500 is the Motorola processor core that is compliant with the PowerPC Book E architecture). For these industrial designs, IDAP generates high-level estimates for dynamic power dissipation that are accurate with an error margin of less than 22.2% of detailed (layout extracted) SPICE simulations. We apply the tool in three different scenarios: 1) identifying the subblocks that contribute to power significantly; 2) evaluating the effect of bitline-voltage swing on array power; and 3) evaluating the effect of memory bit-cell dimensions on array power.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10/2004; · 1.09 Impact Factor

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