FPGA implementation of a sigma-delta (Σ-Δ) architecture based digital I-F stage for software radio

Abstract

A bandpass sigma-delta (Σ-Δ) modulator architecture based digital I-F stage, suitable for software radio technology is investigated. The I-F stage separates the in-phase and quadrature (I and Q) signals using a single circuit path, thus eliminating any I-Q differences due to component mismatch. The separated I-Q signals can then be used in a subsequent DSP stage such as software FM demodulator that is compatible with digital wireless or FM receiver systems. The performance of the single path circuit in terms of quantization noise and I-Q signal mismatch effects is analyzed in detail. Based on this analysis, criteria for the selection of designing parameters, such as sampling frequency and oversampling ratio are presented. Issues related to hardware realization of the I-F stage using a field programmable gate array (FPGA) are discussed and a system level approach to the design of the FPGA is shown. Although FPGA does not offer optimized hardware implementation when compared to ASIC (application specific integrated circuit), it allows short design time and enables rapid verification of algorithms in hardware.