Chip size estimation based on wiring area
ABSTRACT The placement of modules must be designed considering the routability and area reduction simultaneously. But as they are rather conflicting aims, it is not easy to devise a consistent method. The wiring is done on the routing graph and the compaction on the compaction graph. Therefore, only if these two graphs are so defined to reflect each other, is consistent placement possible. This paper points out the fact that if they are constructed based on the floorplan, these graphs are planar and dual to each other. Since the edges are in one-to-one correspondence, the congestion of wires in the routing graph is directly transformed to the length of the compaction graph. The idea is used for the whole layout design but this paper only describes an application to predict the chip area. Some experiments are also shown to be promising.