Conference Paper

Conditional pre-charge techniques for power-efficient dual-edge clocking

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
DOI: 10.1109/LPE.2002.146709 Conference: Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Source: DBLP

ABSTRACT A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18μm process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper deals with load frequency control study of high, medium and low head single area hydro power system. The gains of proportional-integral-derivative (PID) controller have been optimized using Particle Swarm Optimization with integral squared error (ISE) and integral time absolute error (ITAE) performance index as fitness functions. Simulations are carried out for the same using MATLAB/SIMULINK as a simulation tool.
    Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on; 01/2012
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a novel low power pulse-triggered flip-flop design is presented. Firstly, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple 2-transistor AND gate design is used to reduce the circuit complexity. Secondly, a conditional pulse enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse generation circuit can be reduced for power saving. Various post-layout simulation results based on UMC CMOS 90nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate based FF design, the average leakage power consumption is also reduced by a factor of 3.52.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the whole synchronous circuit. The pulse generator can be shared among many flip-flops to reduce the power dissipation. Firstly, in the Dual edge static pulsed flip-flop suffers from high leakage current leads to more power consumption. Secondly, Dual edge trigger sense amplifier flip-flop having unnecessary transitions which causes power consumption. Thirdly, Dual edge trigger NAND keeper flip-flop keeper technique is used to pull up the voltage to VDD having full swing and this keeper transistor width is high and which consumes more power. The power consumption of the Dual edge nand keeper flip-flop is 347uW. Lastly, Dual edge trigger pulsed flip-flop is introduced by employing a technique called conditional switching for further power reduction. The circuits are designed in a 0.18-um standard CMOS process with a 1.8V power supply voltage.
    Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on; 01/2012


Available from