Conference Paper

Conditional pre-charge techniques for power-efficient dual-edge clocking

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
DOI: 10.1109/LPE.2002.146709 Conference: Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Source: DBLP

ABSTRACT A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18μm process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

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    • "Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). In this scenario, same data throughput can be achieved at half of the clock frequency as compared to single edge triggered Flip-Flops [4]. In other words we can say that double edge clocking can be used to save half of the power in the clock distribution network. "
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    • "Digital Object Identifier 10.1109/TVLSI.2009.2029116 utilizing dual-edge triggering, the flip-flop is capable of sampling data on both rising and falling edges of the clock so that only half the clock frequency is needed to obtain the same data throughput of single edge-triggered flip-flops (SETFFs) [2]. Recently , several low-power high-speed DETFF structures have been proposed [3]–[10]. "
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    ABSTRACT: A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2011; 19(1-19):1 - 9. DOI:10.1109/TVLSI.2009.2029116 · 1.36 Impact Factor
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    • "To eliminate these charging/discharging activities, a pMOS transistor is inserted in the precharging path, which will prevent the precharging of node in case the data input is stable HIGH. Flip-flops CPFF [12], DE-CPFF [13], and CP-SAFF [14] employ this technique; they are shown in Fig. 2(a)–(c) respectively. For example, in CP-FF and dual-edge clocking conditional precharge flip-flop (DE-CPFF) the control signal is whereas in conditional precharge sense-amplifier flip-flop (CP-SAFF) the control signal is the data input . "
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    ABSTRACT: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2004; 12(5-12):477 - 484. DOI:10.1109/TVLSI.2004.826192 · 1.36 Impact Factor
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