Conference Paper
Conditional precharge techniques for powerefficient dualedge clocking
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
DOI: 10.1109/LPE.2002.146709 Conference: Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on Source: DBLP

Conference Paper: Load frequency control based on Particle Swarm Optimization in a single area hydro power system under various heads
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ABSTRACT: This paper deals with load frequency control study of high, medium and low head single area hydro power system. The gains of proportionalintegralderivative (PID) controller have been optimized using Particle Swarm Optimization with integral squared error (ISE) and integral time absolute error (ITAE) performance index as fitness functions. Simulations are carried out for the same using MATLAB/SIMULINK as a simulation tool.Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on; 01/2012 
Conference Paper: Low power dual edge triggered flipflop
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ABSTRACT: Flipflops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the FlipFlop is an important element to determine the performance of the whole synchronous circuit. The pulse generator can be shared among many flipflops to reduce the power dissipation. Firstly, in the Dual edge static pulsed flipflop suffers from high leakage current leads to more power consumption. Secondly, Dual edge trigger sense amplifier flipflop having unnecessary transitions which causes power consumption. Thirdly, Dual edge trigger NAND keeper flipflop keeper technique is used to pull up the voltage to VDD having full swing and this keeper transistor width is high and which consumes more power. The power consumption of the Dual edge nand keeper flipflop is 347uW. Lastly, Dual edge trigger pulsed flipflop is introduced by employing a technique called conditional switching for further power reduction. The circuits are designed in a 0.18um standard CMOS process with a 1.8V power supply voltage.Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on; 01/2012  [Show abstract] [Hide abstract]
ABSTRACT: In This paper, a novel high performance pulse Triggered flip flop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. A conditional pulseenhancement technique is devised to speed up the discharge along the critical path only when needed. The proposed EPTL avoids unnecessary internal node transitions to improve the power consumption as compared to previously circuit. We also design 16bit Shift Resistor using proposed EPTL. The proposed design features the best power consumption and powerdelayproduct performance as compared to the other three previously designed FF’s. Its maximum power saving compared to the conventional PFF designs is up to 20% and 16bit shift resistor has 39% power saving compared to previous EPTL based Shift registerInternational Journal of scientific research and management. 05/2014; 2(6):970973.
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