Conference Paper

Conditional pre-charge techniques for power-efficient dual-edge clocking

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
DOI: 10.1109/LPE.2002.146709 In proceeding of: Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Source: DBLP

ABSTRACT A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18μm process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

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