Conference Paper

Conditional pre-charge techniques for power-efficient dual-edge clocking

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
DOI: 10.1109/LPE.2002.146709 Conference: Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Source: DBLP

ABSTRACT A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18μm process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

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    ABSTRACT: A new technique for pulse generation circuit of dual edge triggered flip flop for low power is presented in this paper which enables the flip flop to be operated at 1.2 V. By incorporating a new fast latch and employing conditional pre-charging, dual edge triggered flip flop is capable of achieving low power consumption that has smaller delay. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16% and 27.36% less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. Proposed flip-flop is capable to reduce Clock to output delay up to 44% of that of DSPFF.
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    ABSTRACT: In This paper, a novel high performance pulse Triggered flip- flop design is presented. The proposed design reduces the number of transistors stacked in the discharging path and also reduces the overall switching delay. A conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. The proposed EPTL avoids unnecessary internal node transitions to improve the power consumption as compared to previously circuit. We also design 16-bit Shift Resistor using proposed EPTL. The proposed design features the best power consumption and power-delay-product performance as compared to the other three previously designed FF’s. Its maximum power saving compared to the conventional P-FF designs is up to 20% and 16bit shift resistor has 39% power saving compared to previous EPTL based Shift register
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