Address code optimization using code scheduling for digital signal processors
ABSTRACT We propose an effective address code generation algorithm for digital signal processor (DSP) to minimize the number of addressing instructions. Unlike previous works in which code scheduling and offset (address) assignment are performed sequentially without any interaction between them, our work tightly couples code scheduling with offset assignment to exploit scheduling on optimizing addressing instructions more effectively. We accomplish this by proposing a new code scheduling algorithm that leads to an efficient sequence of variable accesses, minimizing addressing instructions. Experimental results with benchmark DSP programs show average improvements of 23.7% and 47.1% in the address code size and a naive storage assignment algorithm, respectively.
- Softw., Pract. Exper. 01/1992; 22:101-110.
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ABSTRACT: Over the last decade, significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of generalpurpose computing, and more specifically the SPEC benchmark suite. At the same time, a number of microprocessor architectures have emerged which have VLIW and SIMD structures that are well matched to the needs of the ILP compilers. Most of these processors are targeted at embedded applications such as multimedia and communications, rather than general-purpose systems. Conventional wisdom, and a history of hand optimization of inner-loops, suggests that ILP compilation techniques are well suited to these applications. Unfortunately, there currently exists a gap between the compiler community and embedded applications developers. This paper presents MediaBench, a benchmark suite that has been designed to fill this gap. This suite has been constructed through a ...11/1997;
Conference Proceeding: Storage Assignment to Decrease Code Size.01/1995