Address code optimization using code scheduling for digital signal processors
Dept. of Electr. Eng. & Comput. Sci. & Adv. Inf. Technol. Res. Center, Korea Adv. Inst. of Sci. & Technol.DOI: 10.1109/ISCAS.2002.1010745 Conference: Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, Volume: 5
Source: IEEE Xplore
We propose an effective address code generation algorithm for digital signal processor (DSP) to minimize the number of addressing instructions. Unlike previous works in which code scheduling and offset (address) assignment are performed sequentially without any interaction between them, our work tightly couples code scheduling with offset assignment to exploit scheduling on optimizing addressing instructions more effectively. We accomplish this by proposing a new code scheduling algorithm that leads to an efficient sequence of variable accesses, minimizing addressing instructions. Experimental results with benchmark DSP programs show average improvements of 23.7% and 47.1% in the address code size and a naive storage assignment algorithm, respectively.
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