Conference Paper

Improving compression ratio, area overhead, and test applicationtime for system-on-a-chip test data compression/decompression

Dept. of Electron. & Comput. Sci., Southampton Univ.
DOI: 10.1109/DATE.2002.998363 Conference: Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Source: IEEE Xplore

ABSTRACT Proposes a new test data compression/decompression method for systems-on-a-chip. The method is based on analyzing the factors that influence test parameters: compression ratio, area overhead and test application time. To improve compression ratio, the new method is based on a variable-length input Huffman coding (VIHC), which fully exploits the type and length of the patterns, as well as a novel mapping and reordering algorithm proposed in a pre-processing step. The new VIHC algorithm is combined with a novel parallel on-chip decoder that simultaneously leads to low test application time and low area overhead. It is shown that, unlike three previous approaches which reduce some test parameters at the expense of the others, the proposed method is capable of improving all the three parameters simultaneously. An experimental comparison on benchmark circuits validates the proposed method

0 Followers
  • Source
    • "Other test compression techniques do not require circuit structural information and are more suitable for Intellectual Property (IP) cores. Examples of these techniques include statistical coding [19] [20], selective Huffman coding [21], run-length coding [22], mixed run-length and Huffman coding [23], Golomb coding [24], frequency-directed run-length (FDR) coding [25], alternating run-length coding using FDR [26], geometric-primitive-based compression [27], MTC coding [28], variable-input Huffman coding (VIHC) [29], 9-coded compression [30] and dictionary-based coding [31- 32]. Test data compression techniques in this class can be further classified as being either test-dependent or test-independent. "
    [Show abstract] [Hide abstract]
    ABSTRACT: One of the major challenges in testing a system-on-a-chip is dealing with the large volume of test data. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0s. It is demonstrated that higher test data compression can be achieved based on encoding both runs of 0s and 1s. An extension to the FDR code is proposed and by experimental results its effectiveness in achieving a higher compression ratio is demonstrated.
    IET Computers & Digital Techniques 06/2008; 2(3-2):155 - 163. DOI:10.1049/iet-cdt:20070028 · 0.36 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper discusses an integrated solution for reducing the volume of test data for deterministic system-on-a-chip testing. The proposed solution is based on a new test data decompression architecture which exploits the features of a core wrapper design algorithm targeting the elimination of useless test data. The compressed test data can be transferred from the automatic test equipment to the on-chip decompression architecture using only one test pin, thus providing an efficient reduced pin count test methodology for multiple scan chains-based embedded cores. In addition to reducing the volume of test data, the proposed solution decreases the control overhead, test application time and power dissipation during scan. Further, it also requires lower on-chip area when compared to the testing scenarios which employ decompression architectures for every scan chain and it eliminates the synchronization overhead between the automatic test equipment and the system-on-a-chip. Moreover, the proposed solution is scalable and programmable and, since it can be considered as an add-on to a test access mechanism of a given width, it provides seamless integration with any design flow. Thus, the proposed integrated solution is an efficient low-cost test methodology for systems-on-a-chip.
    Test Conference, 2002. Proceedings. International; 02/2002
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper suggests a novel architecture for a reconfigurable accelerator for computations over discrete vectors. The number of executed operations is limited but they can arbitrarily be chosen from a practically unlimited set of feasible operations. The software model and hardware implementations of the accelerator are discussed in detail.
    2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey; 01/2003
Show more