Conference Proceeding

Improving compression ratio, area overhead, and test applicationtime for system-on-a-chip test data compression/decompression

Dept. of Electron. & Comput. Sci., Southampton Univ.;
02/2002; DOI:10.1109/DATE.2002.998363 ISBN: 0-7695-1471-5 In proceeding of: Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Source: IEEE Xplore

ABSTRACT Proposes a new test data compression/decompression method for systems-on-a-chip. The method is based on analyzing the factors that influence test parameters: compression ratio, area overhead and test application time. To improve compression ratio, the new method is based on a variable-length input Huffman coding (VIHC), which fully exploits the type and length of the patterns, as well as a novel mapping and reordering algorithm proposed in a pre-processing step. The new VIHC algorithm is combined with a novel parallel on-chip decoder that simultaneously leads to low test application time and low area overhead. It is shown that, unlike three previous approaches which reduce some test parameters at the expense of the others, the proposed method is capable of improving all the three parameters simultaneously. An experimental comparison on benchmark circuits validates the proposed method

0 0
 · 
0 Bookmarks
 · 
25 Views
  • Source
    [show abstract] [hide abstract]
    ABSTRACT: Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, and thus the amount of compression that can be achieved with a linear decompressor is directly limited by the number of specified bits in the test data. The paper describes a scheme in which a nonlinear decoder is placed between the linear decompressor and the scan chains. The nonlinear decoder uses statistical transformations that exploit correlations in the test data to reduce the number of specified bits that need to be produced by the linear decompressor. Given a test set, a procedure is presented for selecting a statistical code that effectively "compresses" the number of specified bits (note that this is a novel and different application of statistical codes from what has been studied before and requires new algorithms). Results indicate that the overall compression can be increased significantly using a small nonlinear decoder produced with the procedure described in this paper.
    20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA; 01/2005
  • Source
    [show abstract] [hide abstract]
    ABSTRACT: A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.
    VLSI Test Symposium, 2005. Proceedings. 23rd IEEE; 06/2005
  • Source
    [show abstract] [hide abstract]
    ABSTRACT: We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip decompression. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed scheme reduces testing time and allows the use of a slower tester. Results on test application time for the ISCAS'89 circuits are obtained using an ATE testbench developed in VHDL to emulate AT E functionality.
    Journal of Electronic Testing 01/2004; 20:199-212. · 0.45 Impact Factor

P.T. Gonciari