Conference Paper

D/A conversion: Amplitude and time error mapping optimization

Mixed-signal Microelectron. Group, Tech. Univ., Eindhoven
DOI: 10.1109/ICECS.2001.957610 Conference: Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, Volume: 2
Source: IEEE Xplore

ABSTRACT In this paper, an investigation is made of how the topology
dependent amplitude errors and time skews affect the output signal
distortion of a digital to analog converter (DAC). The time
nonlinearities caused by topology are highlighted as another obstacle
that limits the spurious free dynamic range (SFDR). It is shown that
proper error mapping can boost up the SFDR in addition to the obtainable
static accuracy. A general framework and analysis of the error transfer
is given and results of an efficient optimization algorithm are
presented

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    • "This paper derives a set of conditions that are sufficient for an arbitrary DEM technique to eliminate pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in high-resolution DACs. It is demonstrated in [13] that a specific type of DEM can be used to eliminate mismatch-induced timing errors as sources of nonlinear distortion, and proposed in [14] and [15] that mapping, Fig. 1. High-level system diagram of a 3-bit power-of-two-weighted DAC. "
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    ABSTRACT: This paper shows analytically and experimentally that properly-designed dynamic element matching (DEM) eliminates pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion in high-resolution DACs. A set of sufficient conditions on the DEM encoder that ensure this effect, and a specific segmented DEM encoder that satisfies the sufficient conditions are presented. Unlike most previously published DEM encoders, the new DEM encoder's complexity does not grow exponentially with the number of bits of DAC resolution, so it is practical for high-resolution Nyquist-rate DACs. These analytical results are demonstrated experimentally with a 0.18 mum CMOS 14-bit DAC IC that has a sample rate of 100 MHz and worst case, single and two-tone spurious-free dynamic ranges of 83 dB and 84 dB, respectively, across the Nyquist band.
    IEEE Journal of Solid-State Circuits 10/2008; 43(9-43):2067 - 2078. DOI:10.1109/JSSC.2008.2001931 · 3.11 Impact Factor
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    ABSTRACT: Timing errors become dominant in dynamic performance of high-speed and high-resolution current-steering Digital-to-Analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, two smart calibration/correction techniques, based on on-chip timing error measurement, are proposed. Simulation results show that with mapping technique, the Spurious-free Dynamic Range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatch-related timing errors.
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    ABSTRACT: This paper addresses the timing and switching errors of Switched Current (SI) Digital to Analog Converters (DAC) aimed to be used in high speed multi-bit ΣΔ and Nyquist Converters. The analysis is based on an error-analysis framework, according to which all the errors are classified dependent on their properties with respect to the time and spatial domains. Examples are presented that are related with significant problems occuring during implementation, and with overall requirements of high speed multi-bit ΣΔ modulators.
    12/2001: pages 205-233;
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