Analog design for reuse-case study: very low-voltage ΔΣmodulator

Abstract

This paper presents the complete design methodology of a very low-voltage ΔΣ third-order modulator from high-level specifications down to layout. Behavioral models taking into account cell nonidealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover the same design knowledge has been successfully reused in another fourth-order modulator

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Analog Design for Reuse - Case Study: Very Low-voltage ∆Σ Modulator
Mohamed Dessouky†, Andreas Kaiser‡, Marie-Minerve Lou¨ erat†and Alain Greiner†
†Universit´ e Paris VI, Lab. LIP6. 4, Place Jussieu. 75252 Paris Cedex 5. France
‡IEMN-ISEN, UMR CNRS 8520. 41, Bld. Vauban. 59046 Lille Cedex. France
Mohamed.Dessouky@ieee.org
Abstract
This paper presents the complete design methodology
of a very low-voltage ∆Σ third-order modulator from high-
level specifications down to layout. Behavioral models tak-
ing into account cell non-idealities are developed and used
to map performance specifications to lower levels. Empha-
sis has been made on eventual design reuse through design
plans and layout templates in a layout-oriented circuit de-
sign approach. The modulator has been designed for two
different technologies demonstrating the suitability of the
methodology for very high performance mixed-signal cir-
cuits. Moreover, the same design knowledge has been suc-
cessfully reused in another fourth-order modulator.
1. Introduction
The complexity of IC’s being designed nowadays is
continuously increasing as advances in process technology
make it possible to create mixed-signal integrated SoC de-
signs. As SoC’s are becoming larger, the only way to effi-
ciently design such dense SoC’s is by embeddingIP blocks.
Ideally, these cores should be reusable, pre-characterized
and pre-verified. IC foundries and IP providers offer lay-
outs for commonly-used blocks. The problem is that the
analog spacecannotbe fully covered by any finite library of
blocks. An alternative approach consists of developing spe-
cific block synthesis tools [1] [2] which couple optimiza-
tion with a knowledge database continuously updated and
reused by the IP provider. Block generator development,
however, takes a considerable effort and time. It must be
justified by an extensive use of the generator. Design reuse
based on an original working design has been investigated
both through qualitative reasoning [3] and analog synthe-
sis [4]. The above approaches treat only the sizing phase
of the design, the layout is considered as a separate phase
handled with dedicated tools.
Yet the most efficient way to generate reusable IP’s is
by incorporating appropriate information, concerning both
circuit design and layout, in the original design methodol-
ogy. This ensures a first-pass silicon since the original de-
sign considerations of the original working circuit are all
respected. This is made possible through the use of design
plans which include a close interaction between sizing and
layout templates [5].
In this work, this approach is introduced through a de-
mandingapplicationin orderto showits generality andsuit-
ability even to state of the art designs. The complete design
experience of a very low-voltage (1V) third-order ∆Σ mod-
ulator [6] is presented. Switched-capacitor (SC) operation
in standard CMOS has been achieved using a special low-
voltage bootstrapped switch that allows rail-to-rail signal
switching. A modified low-voltage fully-differential opamp
has been employed [7]. The circuit shows the feasibility of
very low-voltage high performance circuits using common
SC techniques.
While the tools supporting the methodology have been
presented by the authors [5], [8] , [9], as well as circuit re-
sults [6], [7], so far no paper has been published to present
an overall view of the design methodology. The use of hi-
erarchical sizing and procedural layout have enabled to ex-
plore a large design space in the presence of layout para-
sitics. The developed behavioral models, sizing procedures
and layout templates have also allowed to resynthesize the
same design in anothertechnology. Moreover, they have al-
lowed to redesign a fourth-order modulator with a different
topology based on the same building blocks.
2. Methodology and Tools
The modulator design process contains four major steps:
1. High-Level Synthesis:
mance goal, the most suitable modulator architecture
and oversampling ratio (OSR) are chosen followed
by modulator coefficient determination. During this
phase usually a large number of simulations are done
Starting from the perfor-

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on the functional level where ideal models are used for
the building blocks.
2. Performance Parameter Mapping: Now that the ar-
chitecturehasbeenfixed,modelsthatdescribethenon-
ideal behavior of the modulator building blocks are
built and used to investigate the feasibility of the cho-
sen architecture on the circuit level. This also leads to
performance parametermapping from the systemlevel
to the building blocks transistor level.
3. Low-Level Synthesis: In this step each block is de-
signed according to the performance specificationsde-
termined in thepreviousstep. Synthesisofthebuilding
blocks is done using the CAD tools and methodology
described in [5]. For each block:
? Thecompletedesignprocedureis incorporatedin
the knowledge-basedsizing tool COMDIAC [9].
Hierarchical sizing facilitates this step by re-
using existing circuit building blocks such as dif-
ferential pairs and OTA’s.
? The layout template is described using the layout
language CAIRO [8]. The code is independent
of transistor sizes and technology. A parasitics
calculation mode allows layout parasitics to be
taken into account during sizing.
4. PhysicalDesign: Thecompletelayoutis generatedus-
ing the layout templates in a layout generation mode.
3. High-Level Synthesis
Σ
a1
1
z-1
Σ
1
z-1
Σ
1
z-1
DAC
a2
b2
a4
b3b1
a3
XY
---
Figure 1. Modulator topology
The goal of this circuit is to achieve very low-voltage
operation (VDD
(around 14 bits) for a digital-audio signal.
Fig. 1 shows the block diagram of the modulator. It
is based on a one-bit chain of integrators with distributed
feedback topology. Modulator coefficients have been de-
termined with the help of the Delta-Sigma Toolbox [10] for
MATLAB, according to the design procedure given in [11].
? 1V) of a high resolution ∆Σ modulator
4. Performance Parameter Mapping
Cell non-idealities lead to quantization noise leakage
and degrade the overall signal-to-noise ratio (SNR). Study-
v1
CS
vin
vout
CI
gm v1og
(a) Sampling phase
v1
CS
vout
CI
gm v1
og
(b) Integration phase
Figure 2. SC integrator
ing their effect also provides mapping of high-level perfor-
mance specifications to individual block ones.
4.1. Opamp Finite Gain and Frequency
An approach similar to [12] is used. The model is based
on the simple one-pole amplifier shown in Fig. 2, whose
transfer function is given by :
H
?z ??
gz
?1
1
? pz
?1
(1)
where
g
?CS
CIρi
Ad0βs
1
?1
?δi
??
p
?ρi
ρs
?
1
?δi
?
1
?ρs
ρi
??
(2)
ρs
?
?Ad0βs
?
ρi
?
Ad0βi
1
?Ad0βi
(3)
where Ad0
tion phases feedback factors. The parameter δirepresents
the settling error in the integration phase. It is expressed by
? gm
?go, βsand βiare the sampling and integra-
δi
? exp
?
?gm
CS
?Ti
ρi
?
(4)
where Tiis the time available for integration. The factor
gm
amplifier during the integration phase. The above model
does not include neither the input parasitic capacitance of
the amplifier(Cip) northe parasitic output capacitance. Fur-
thermore, the used amplifier is actually a two-stage one [7]
having its closed-loop pole determined by an internal com-
pensation capacitance. However, if one tries to model these
effects, the analysis becomes very complicated. One can
preserve the previous simple model and change only the
most inaccurately modeled factors [12], such that
?CSrepresents the closed loop dominant pole pCLof the
βs
?
CI
CI
?Cip
?
βi
?
CI
CI
?Cip
?CS
(5)
In addition,the exponentialfactorin equation(4) is strongly
affected by the parasitic capacitances. Equation (4) can still
be used with pCL
? βiωt, where ωtis the GBW of the two

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204060 80100
50
60
70
80
90
Opamp Gain (dB)
SNR (dB)
•
↓
(a) SNR-opamp gain
0246
75
80
85
90
95
Opamp GBW/fs
SNR (dB)
•
↓
(b) SNR-GBW/fs
Figure 3. Simulation results
stage amplifier. Obviously, these approximations neglect
the effect of high frequency poles and zeros on the settling
performance of the amplifier. This is true for a sufficiently
high phase-margin.
Theabovemodelis thenemployedin discretetime simu-
lations. Same non-idealities are consideredin all amplifiers.
A sinusoidal input of relative amplitude 0.5 and frequency
3.2 kHz is used. First assumingan infinite opampGBW fre-
quency(ft),i.e. δi
overall SNR is studied. Fig. 3(a) shows the results of such
simulations. A gain of 40dB is then sufficient for preserv-
ing the SNR. In our design a gain of 70dB has been chosen
for the first opamp and 60dB for the second and third ones.
This high gain is chosen to avoid any performance degra-
dation and to reduce the effect of non-linearities. Using the
above amplifier gains, Fig. 3(b) shows the variation of the
SNR with ft. Simulations show that an ft
the sampling frequency is sufficient. To have some margin,
a ratio of 3.5 is chosen.
?0,the effectofthe amplifiergainonthe
? 2fswhere fsis
4.2. Opamp Slew Rate
According to the integrator first-order model presented
in the previous section, the time domain response of the in-
tegrator output during the integration phase is given by
Vosf
?t
??Vo1
?Vstep
?
1
?exp
?
?1
ρi
t
τ
??
(6)
where Vo1 represents the leakage of the integrator stored
valuedue to the amplifierfinite gain andGBW andassumed
constant for this analysis,
Vstep
?Vin
?0 ?CS
CIρi,
τ
?
1
pCL
?
1
βiωt
(7)
From Fig. 4, the slewing output can be described by
Vos
?t
??
?SR?t
V1
0
td
?t
? td
?V2
?
1
?exp
?
?1
ρi
t
?td
τ
??
?t
? Ti
(8)
00.511.522.533.54
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
τ
t /
d
step
V2/V
step
V1/V
step
Vo/V
CL
CL
t/τ
Vosf
Vos
Figure 4. Slew-free & and slewing outputs
where V1 and V2 are defined as shown in Fig. 4. Equating
the slope of both sections at t
? td, we have
V2
? SR?τ ?ρi
(9)
and usingVstep
?V1
?V2
? SR?td
?V2, we obtain
td
?Vstep
SR
?τ ?ρi
(10)
Fig. 5 shows an integrator model based on the above
analysis. Vstep represents the integrator output consider-
ing no frequency limitations. The parameters ginf and pinf
are given by equation (2) with δi
slewing-freeintegratoroutputtakinginto accountfrequency
limitations. The parameters gsfand psfare given by equa-
tion (2). The SLEW block models the slewing behavior of
the integrator: Bycalculating tdfrom equation(10), the out-
put can be determined according to the slewing state:
? 0. Vsf represents the
? if td
? 0, then the output is slew free,
? if 0
re-enters eventually in the linear region.
? td
? Ti, then slewing occurs but the integrator
? if td
?Ti, the integratorremains slewing during the en-
tire integration period and the output is given by SR?Ti.
A hard limiter is used to model the integrator output satura-
tion levels.
Using the amplifier gain and GBW frequency calculated
in the previous section and the above integrator model,
Fig. 6 shows the variation of the SNR with the amplifier
SR. A SR of 1 ?3Vref
?Tshas been chosen,where Ts
? 1 ?fs.
1/z
gsf
ginf
psf
pinf
Von-1
?
?
?
?
?
?
?
?
?
?
?
?
SLEW
Vsf
Σ
Σ
ViVo
+
+
+
+
Vstep
Limiter
Figure 5. Integrator model

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1234
50
60
70
80
90
Opamp SR/(Vref/Ts)
SNR (dB)
•
↓
Figure 6. Simulation results, SNR vs. SR
0 0.2
Comparator offset/Vref
0.40.6
70
75
80
85
90
95
SNR (dB)
(a) SNR-offset
0.02
Comparator hysteresis/Vref
0.040.06 0.080.1
82
84
86
88
90
92
SNR (dB)
(b) SNR-hysteresis
Figure 7. Simulation results
4.3. Comparator Offset and Hysteresis
Fig. 7(a) shows the effect of the comparator offset volt-
age. The effect of the offset is greatly reduced by the feed-
back loop of the modulator such that an offset of half of the
reference voltage can still be tolerated. However,hysteresis
is more critical. Fig. 7(b) shows that the ratio between Vhys
and the reference voltage must be kept below 0.05.
5. Low-Level Synthesis and Design
In this phase, the analytical equations used to size the
building blocks starting from the performance specifica-
tions determined in section 4, are derived. In order to be
used in COMDIAC, these equations need to be as accu-
rate as possible. All transistor currents, transconductances
and capacitancesare calculated using the same model equa-
tions as that used in the circuit simulator and implemented
in COMDIAC.
Fig.8 showsthemodulatordesignflowwith emphasison
the low-levelsynthesisstep. Starting fromtherequiredSNR
performance, both the quantization noise and circuit noise
are determined. The in-band noise power must be domi-
nated by the circuit noise rather than the quantization noise
in order to minimize the total power consumption. Quan-
tization noise is determined during high-level synthesis by
the chosen architecture and OSR (section 3). The circuit
noise is further decomposed to KT
noise. Due to the very low coefficient of the first integrator
(a1) the amplifier noise becomes dominant. The amplifier
?C noise and amplifier
Quantization Noise
Signal BW
Architecture + OSR
CoefficientsSampling Frequency
Performance Parameter Mapping
Amplifier Gain, GBW, SR
Circuit Noise
Capacitance Values
Sampling CCompensation C
SNR
Integrator
Sizing
Switch Sizing
Opamp NoiseKT/C Noise
Layout Generation
Layout Template
Amplifier Sizing
Figure 8. Modulator design flow
thermal noise power depends directly on the compensation
capacitorCC, butsinceit alsodependsonthe amplifiernoise
excess factor γth, which is not known before the complete
amplifier design, fine tuning of the compensation capacitor
value is thus needed during the amplifier sizing process. In
fact, the calculated CCsets the minimal value for the com-
pensation capacitor which also controls the opamp phase
margin. On the other hand, the switch thermal noise power
is mainly determined by the value of the input sampling ca-
pacitor. Starting from the modulator coefficients and taking
into accountintegrator scaling, all capacitorvalues are then
determined.
Performance parameter mapping is then performed as
described in section 4 leading to values for the opamp DC
gain, GBW and SR, as well as the comparator offset and
hysteresis that avoid noise leakage. Integrator sizing then
follows as described in the following section.
5.1. Integrator Sizing in COMDIAC
Fig.9showsthe integratorsizingplan. In ourdesignpro-
cedure, there are two sets of input parameters; those deter-
mined directly by the previoushigh-levelanalysis and those
used for design optimization. The first set, shown horizon-
tally in Fig. 9, includes:
? The maximum input signal amplitude (Umax).
? The sampling frequency (fs) and the integration phase
duty cycle.
? The opamp gain, GBW, and SR.
? Minimum opamp compensation capacitance (CC).
? Theintegrationandsamplingcapacitances(CIandCS).

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SRGBWGain Noise
Gain GBWSRUmax
f s& duty cycle
Layout Template
Load C
Power ConsumptionDynamic RangeSettling
Capacitance Values Compensation C
Transistor Bias (Veg)
Phase Margin
Amplifier Sizing (Fig. 10)
High-level Synthesis
Opamp Input C
Circuit Noise
Figure 9. Integrator sizing
While the secondset, shownvertically on the right ofFig.9,
includes:
? The phase margin (PM).
? Transistor bias voltages VEGandVDS.
The integrator sizing module uses the opamp module as a
building block. The opamp load CLis calculated taken into
account the loading of the integrator feedback network as
given by
CL
?
?CS
CS
?Cip
?CI
?Cip
?CI
?CIbp
(11)
whereCIbpis the integration capacitorbottom-plate capaci-
tance. SinceCLdepends onCipwhich is only calculated af-
ter sizing, two or more iterations are needed to find CL. The
opamp calculated performance parameters are then used to
calculate those of the integrator namely the settling perfor-
mance,the dynamicrangeandthe total powerconsumption.
Shaded input parameters on the right of the figure, namely
transistor bias voltages,are used for performance optimiza-
tion as explained in the next section. The optimization goal
was to minimize the power consumption under a given set-
tling and dynamic range performance.
A layout template is used to calculate the associated lay-
outparasitics. During sizing,layoutparasiticsare alsotaken
into account. This includes exact transistor diffusion after
the calculation of parallel elements (M), routing and capac-
itor bottom-plate capacitances.
5.2. Opamp Sizing in COMDIAC
Thecomplexityofthesizingproblemresidesin its multi-
dimensional design specification and variable spaces. Four
types of independent variables can be defined for a given
opamp:
1. the bias current I,
2. transistor biasing voltagesVEG
?VGS
?VTHandVDS,
ε
Performance
Comparison
Parasitics
Loop
YES
|GBW_cal-GBW|<
NO
L=Lmin
L=L+step
Loop
I=I*GBW/GBW_cal
(DC Gain, SR, Noise, ...)
Netlist + Layout
Sizing
Well sizes
Routing capacitance
(# folds, diff. sharing, ...)
Process
Parameters
Bias Point
VEG, VDS
Netlist Template
(from library)
Input Specifications:
VDD, CL, PM, GBW, SR
DC Gain, Output Excursion, Noise
Calculate all Performance Spec.
Device layout style
YES
NO
YES
Layout Template Parasitics Calculation
NO
Parasitics Convergence
YES
PM >= PM_cal
I=Iinit=f(GBW)
Calculate PM_cal & GBW_cal
NO
Interactive
VDD, GBW, CL, PM
Calculate transistor W’s
Calculate small signal parameters
Figure 10. Opamp sizing
3. technology parameters, and
4. transistor lengths L.
By fixing the current and biasing voltages, only transistor
lengths should be varied in order to satisfy a given per-
formance specifications. The phase-margin (PM) and the
gain-bandwidth product (GBW) have been chosen as the
main characteristics to be satisfied. Other specifications
canbe realized interactively by modifying transistorbiasing
points. Fig. 10 describes the sizing procedure. A minimal
set of specifications are defined,this includes:
? the supply voltageVDD,
? the gain-bandwidth product,
? the phase margin,
? the load and compensation capacitances,
in addition to the biasing voltageVDSandVEGof each inde-
pendent transistor which are also held constant during the
sizing loop (since VTHchanges with transistor lengths dur-
ing sizing, the effective gate-source voltage VEG
VTH is held constant rather than VGS).
bias current is estimated from the given GBW. All tran-
sistor lengths are set to their corresponding minimal value
? VGS
?
First, an initial