Conference Proceeding

A 2.05 um2 full CMOS ultra-low power SRAM cell with 0.15 nm generation single gate CMOS technology

SRAM-1 Team, Samsung Electron. Co. Ltd., Yongin City;
02/2000; DOI:10.1109/IEDM.2000.904386 ISBN: 0-7803-6438-4 pp.579 - 582 In proceeding of: Electron Devices Meeting, 2000. IEDM Technical Digest. International
Source: IEEE Xplore

ABSTRACT We have developed a 2.05 um2 full-CMOS ultra-low power
SRAM Cell, which is probably the world-smallest, using 0.15 um
generation single gate CMOS technology. The technology includes i) 0.15
um direct contact (to active region and gate poly) implemented by phase
shift mask (PSM) and the shrinkage of contact by photo-resist (PR)
reflow, ii) W-damascened local interconnection with 0.30 um pitch, iii)
careful optimization of 0.17 um gate length buried channel (BC) pMOS to
minimize the leakage current, while excludes self-aligned contact,
Co-salicide, and rapid thermal annealing (RTA)

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Keywords

active region
 
careful optimization
 
Co-salicide
 
gate poly
 
generation single gate CMOS technology
 
leakage current
 
photo-resist
 
PSM
 
rapid thermal annealing
 
RTA
 

J H Jang