Cross coupled transconductance cell with improved linearity range

Abstract

A novel variation of the cross-coupled operational
transconductance cell is presented in this paper. The conventional
cross-coupled cell has a differential input linearity range that is
dependent on the control voltage. The proposed design removes that
restriction while allowing the same tunability using the control
voltage. Its input may also be single or fully differential unlike the
conventional cross-coupled cell, which requires a fully differential
input. Results were confirmed using HSPICE simulations

Full text

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Cross Coupled Transconductance Cell with Improved Linearity Range
Brent J. Maundy1, Ivars G. Finvers1, and Peter Aronhime2
1Department of Electrical and Computer Engineering, University of Calgary,
2500 University Drive NW, Calgary, Alberta, Canada T2N 1N4
email: maundy@enel.ucalgary.ca, finvers@enel.ucalgary.ca
2Electrical Engineering Dept., University of Louisville, Louisville, KY 40292, USA
email: pbaron01@homer.louisville.edu
ABSTRACT
A novel variation of the cross-coupled operational
tranconductance cell is presented in this paper. The conventional
cross-coupled cell has a differential input linearity range that is
dependent on the control voltage. The proposed design removes
that restriction while allowing the same tunability using the
control voltage. Its input may also be single or fully differential
unlike the conventional cross-coupled cell, which requires a fully
differential input. Results were confirmed using HSPICE
simulations.
INTRODUCTION
In recent years, the operational transconductance amplifier
(OTA) has received considerable attention in the literature due to
its usefulness and versatility in many filtering and signal
processing applications. To this end numerous techniques on
designing OTAs have been realized using CMOS devices. In the
traditional approach to OTA design the popular source-coupled
differential pair served as the basic voltage-current conversion
element. While this approach exhibits generally good overall
frequency performance its large signal characteristics are non-
linear [1]. Other approaches to emerge recently have included
the use of cross-coupled cells [2-3], composite CMOS transistors
[4-7], composite NMOS transistors [7, 8], and simple CMOS
inverters [9]. The trend towards small feature size and low
supply voltage use have necessitated the use of the
aforementioned techniques and the development of others [10,
11] to address the reduced dynamic range and non-linearity
issues.
This paper introduces a variant of the cross-coupled
transconductance cell [3] combined with a composite differential
pair used in a level-shifting configuration. It maintains the high
linearity of the cross-coupled cell while allowing use with either
single ended input or fully differential input signals. In our
proposed design the transistors are assumed to be in saturation,
and the transconductance is controlled with a voltage. The input
linearity range is independently set by a bias current. HSPICE
simulations confirm all results.
CIRCUIT OPERATION
The basic diagram of the transconductor is shown in Fig. 1. All
like devices are assumed matched. The circuit consists of the
differential pair M1 and M2 connected to two matched transistors
biased at a voltage Vb. In contrast to a standard OTA design M3
and M4 would normally be diode connected n-transistors. The
fact that M3 and M4 are series connected p-transistors establishes
a relationship between the source-to-gate voltage of each
transistor that obeys the simple well-known square law
relationship
(
=−−
(
IVVVVV
apxTpp SGTp
=−−
) =
) =
−
(
(
)
)
ββ
2
2
3
2
(1a)
IVVVVV
bpx TppSG Tp
−ββ
1
2
4
2
(1b)
where βp = Kp(W/L)/2 has its usual meaning, Vx is the voltage
at node x, and we have neglected channel length modulation
effects. VTp is the threshold voltage defined by
VVV
Tp To BS
=+−−
(
)
γφφ
(2)
where VBS is the bulk-source voltage and VTo the threshold
voltage for VBS = 0, γ the bulk threshold parameter, and φ the
strong inversion surface potential. We have assumed for the
moment that all the transistors have their bulk nodes connected to
sources to eliminate the bulk effect. The bulk effect will be
taken into account when considering the threshold modulation
effects in the section following. Eqns. (1a) and (1b) can be
solved to yield the source-to-gate voltages of M3 and M4 as,
V
V
V
V
V
V
SGx
32
=
=
−
−
(3a)
(3b)
SGx
41
,
respectively. Since transistors M5 and M8 have the same gate-
source voltage as M3 and M4 respectively, their drain currents can
be expressed as
IV
(
V
n SGTn
33
2
=
=
−
−
(
)
)
β
β
(4a)
IVV
nSG Tn
44
2
(4b)
Transistors M13 and M14, however, do not share the same gate-to-
source voltage as their M5 and M8 counterparts, but their currents
can likewise be expressed as,
IV
(
VV
nSGb Tn
13
2
=
=
+
+
−
−
(
)
β
β
(5a)
IVVV
nSG b Tn
24
2
)
(5b)
The output current Io = I2 + I3 - I1 - I4 obtained by simple
mirroring and addition can be shown to be
IVV V
1
onb
=−
(
)
2
2
β
.(6)

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This configuration exhibits a linear transconductor of value
gV
m n b
= 2β
that can be tuned by varying Vb.
THRESHOLD MODULATION EFFECTS
Up until this point we have assumed zero bulk effects. In a
standard n-well CMOS technology such as the one that this
circuit was implemented in, the bulk terminal of an n-transistor
with its source level shifted must be tied to ground or VSS. For
that case, Vb will modulate the threshold voltage of M5 and M8
only. If we factor the different threshold voltages into the circuit
of Fig. 1 it can be shown that the resulting transconductance is
given by
(
gVV
mnbb
=++−
)
(
)
2βγφφ
.(7a)
Hence there is an associated error in gm that is proportional to the
square root of Vb. The output current is therefore given by
IVVVVV
onbTn
′ −
Tn
=−
(
)
+
(
)
2
21
β
(7b)
where
is the threshold voltage of M13/M14. Hence the net effect of
threshold modulation is to make the control of gm non-linear with
Vb.
It should also be noted that transistors M5, M8, M13, and M14
form a cross coupled pair whose differential input is
VV
SDSD
34
−
. For the cross-coupled pair [3], it is easy to show
that its linear differential range is limited to Vd < 2|Vcm - Vb -
′
VTn|, where Vcm is the common mode input voltage the inputs
are held at and Vd = V2 - V1. Here V1 and V2 would be the
inputs present to transistors M5/M13 and M8 /M14, respectively if
they formed the core transconductance cell. This input range is
therefore dependent on Vb. In the section following we will
show that the linearity range of the circuit of Fig. 1 is set by the
bias current Ibias and is therefore independent of Vb.
′
VTn is the threshold voltage of transistors M5/M8, and VTn
LINEARITY CONSIDERATIONS
In deriving Eqn. (6) certain assumptions were made that will
affect the linearity of the proposed circuit in any practical design.
The assumptions being:a) All the transistors are always in
saturation, and b) No channel length modulation effects are
present. In this section we shall consider the two assumptions
one at a time.
A.
main transistors and in particular M1 and M2 are operating in
saturation. It can be easily shown that M1-4 will remain in
saturation only if VVV
cmSG sat
<+
1
[
The equations above have all previously assumed that the
and,
VVVVV
d
cmbTp
<−−−
(
)
]
2
max
(8)
where, Vsat is the minimum saturation voltage required across
the current source Ibias. The linear range of operation for the
circuit can be deduced by considering typical voltages at the
source of transistors M3 and M4 as shown in Fig. 2. Fig. 2 also
shows the changes in the gate-source voltages of M5 and M8.
Note that the voltage at the source of M3 (M4) is equal to the
gate-source voltage of M13 (M14), respectively. The maximum
source-to-gate voltage of M3 (M4) is given by
V
I
β
V
bias
P
Tp
max=+
(9)
and the maximum voltage that the source of M3 (M4) attains is
VVb
. These voltages occur when either M1/M3 are on with
M2/M4 off, or vice versa, respectively. In the linear region of
operation Eqns. (1a) and (1b) govern the operation of M1, and
M2. Assuming that V1 = -Vd/2 + Vcm and V2 = Vd/2 + Vcm the
differential voltage Vd is therefore related to VSD3 and VSD4 by
max+
VVVVV
d
SDSD
GS
GS
=−
(
)=−
(
)
34
5
8. (10)
The magnitude of the most negative excursion of Vd can be
found by observing that M8 turns off when VGS8 =
VGS5 = Vmax. In addition, M8 approaches its threshold voltage
prior to M14 because
′
VTn > VTn. The net result of this is that the
magnitude of the most negative excursion of Vd is V
which is dependent on Ibias. By a similar reasoning the most
positive excursion on Vd before M5 turns off will be given by a
similar expression, and the differential voltage for which the
circuit is linear is therefore given by
′
VTn, and
VTn
max−
′
(
)
VV
d<−
′
(
)
max
VTn.(11)
At a first glance, Eqn. (11) shows that the linear range of input
voltages can best be increased by increasing Ibias or by using p-
transistors with low aspect ratios. However, Ibias cannot
increase indefinitely but its maximum value will be set by
IVV
biaspcmb
max max
()
<−β
allowable control bias voltage the circuit sees. A comparison
between Eqns. (11) and (8) will show that with VTp ≅
common mode voltage the circuit should be biased at must satisfy
VVV
cm
d
b
>+
1 5 .
max
differential input voltage that will be present at the inputs to
satisfy Eqn. (11). Finally, note that for VTn < VGS8 <
VTn < VGS5 <
′
VTn the circuit will continue to function but Io will
have increased second order harmonic distortion products
because I4 = 0 or I3 = 0, respectively.
2, where Vbmax is the maximum
′
VTn, the
max. Here Vdmax represents the maximum
′
VTn or
B.
drain currents of the transistors being dependent on the drain
voltage. These effects can be reduced by increasing the channel
length of the devices at the expense of slowing the circuit down.
Channel length modulation effects inherently result in the
SHORT CHANNEL EFFECTS
If speed is of importance in a design, and short channel lengths
must be used, it is worth mentioning that when using a HSPICE
level 28 model for deep sub-micron processes, it was observed

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that Kn could vary significantly between transistors with different
large gate-source voltages. If βn is assigned to transistors
M5/M8, and
′
βn assigned to transistors M13/M14, then, Eqn. (7a)
must be modified to,


22
2
(
n Tnn Tn
V
gV
I
V
mn b
′
β
bias
β
p
Tpnn
=−+




− ′
β
(
)
β
+
′ − ′
)
2 ββ
V
.(12)
The last two terms in Eqn. (12) can be thought of as a correction
factor that is gradually reduced as L increases, because
approaches βn.
′
βn
SIMULATION AND MEASURED RESULTS
The circuit of Fig. 1 was implemented in a 0.35 µm CMOS
process and simulated with HSPICE using a level 28 model. The
supply voltage was set at 3 V and the bias current set at 100 µA.
The common mode voltage was set at half the supply voltage and
the differential voltage changed over half the supply voltage.
The gate widths of the transistors used were M1-4 = 50 µm, M5 =
M8 = M13 = M14 = 5 µm, M11-12 = 35 µm, M6-7 = 80 µm, and M9-
10 = 80 µm. A common channel length of L = 2 µm was chosen
to keep the output resistance of the transistors as high as possible
while minimizing second order effects such as mobility
reduction. No attempt was made to optimize the frequency
response of the OTA. Fig. 3 shows the simulation results of the
transconductance gm for a bias voltage of Vb = 0.6 volts. It
should be noted that as Vd changes the drain currents change
causing changes in the β ’s due to short channel effects. This β
variation contributes to a non-linearity in gm as seen in Eqn. (12)
and shown in Fig. 3. About Vd = 0 and for Kn = 156 µA/V2, K'
= 124 µA/V2, Kp = 59 µA/V2,
VTn = 0.74 V, andVTn = 0.57 V,
the calculated value of gm according to Eqn. (12) was 222.8 µA/V
which represented a 4.4% error in the results obtained from
HSPICE simulations (gm = 213 µA/V). If Eqn. (7) is used to
calculate gm a 28% error results because it assumes that all Kn's
are the same. Vdmax was observed at 0.34 V and confirmed by
Eqn. (11). In a separate simulation one of the circuit's input was
held at the common mode voltage and the other input varied. As
expected the results are identical to that shown in Fig. 3 because
of the differential action of transistors M1-4. In Fig. 4 the bias
voltage is varied from 0.1 V to 0.7 V to show the tunability of the
transconductor. Fig. 4 also shows the experimental results from
the fabricated test chips, which are in close agreement with the
simulated results. In Fig. 5 the normalized gm is plotted against
Vd to illustrate that the differential linear range does not vary for
changing Vb. This was also determined experimentally but is not
shown here. Finally, the implementation of the OTA of Fig. 1in
silicon is shown in Fig. 6. The OTA occupied a core area of 100
x 225 µm2. The quiescent power dissipation of the chip was
observed at 1.38 mW, and for a Vdmax= 0.34 V @1 kHz and Vb
= 0.6 V, the measured second and third harmonic components
were -37.4 dB and -41 dB, respectively from the fundamental.
n
′
CONCLUSION
A novel variation of the well-known cross-coupled cell is
proposed. The key advantages our proposed variant offers are
that its linearity is independent of the bias controlling voltage that
controls the transconductance, and its inputs can be single ended
or fully differential. The latter feature may be particularly useful
as it avoids the employment of extra circuitry to create fully
differential input signals.
ACKNOWLEDGMENTS
The authors would like to acknowledge the support of the Natural
Sciences and Engineering Research Council (NSERC) of Canada
and the Canadian Network of Centres of Excellence in
Microelectronics (Micronet).
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?2
?1
?b
?bias
?DD
?DD
?DD
?DD
?DD
?5
?3
?1
?2
?8
?4
?6
?7
?13
?9
?11
?10
?12
?0
?1
?3
?4
?2
?14
x
?a
?b
Figure 1. The proposed transconductor circuit.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-1.5 -1-0.5 00.5 11.5
Voltage (V)
Vd (Volts)
VSD3 = VGS13
VGS5
VMAX
VMAX + VB
VTn
VTn
'
VSD4 = VGS14
VGS8
Figure 2. Typical variation in the gate-source voltages and drain
source voltages in the transconductor in response to the
differential input voltage.
100
120
140
160
180
200
220
240
-0.4 -0.2 00.2 0.4
gm(µA/V)
Vd(volts)
Figure 3. gm versus differential input voltage for a bias voltage
Vb = 0.6 volts (solid line). The dashed line represents the
theoretically predicted gm result at Vd = 0.
0
50
100
150
200
250
00.1 0.20.30.40.5 0.60.7 0.8
gm(µA/V)
Vb(Volts)
Figure 4. Plot of gm versus Vb. Solid lines and dashed lines
represent simulated and measured responses, respectively.
0.2
0.4
0.6
0.8
1
1.2
-0.4-0.2 00.20.4
Vb = 0.1V
Vb = 0.2V
Vb = 0.3V
Vb = 0.5V
Vb = 0.7V
Normalized gm(µA/V)
Vd (volts)
Figure 5. Normalized gm versus differential input voltage for
varying values of bias voltage to illustrate the linear differential
range.
Figure 6. Layout of the OTA