Conference Paper

A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter

Syst. LSI Div., Samsung Electron. Co., Yongin
DOI: 10.1109/ISCAS.2000.857124 Conference: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 1
Source: IEEE Xplore

ABSTRACT A calibration-free 3.3 V 14-bit 10 MSPS pipelined
analog-to-digital (A/D) converter was implemented using a 0.35 μm
CMOS technology. The ADC utilizes a 4-stage pipelined architecture with
a wideband sample and hold amplifier and achieves the highest resolution
reported to date at 3.3 V 10 MHz. The proposed hybrid capacitor
switching technique of one/two feedback capacitors is applied to improve
the linearity which is limited by component mismatch depending on the
process. Since the proposed technique can be implemented by simple
circuit compared with previous self-calibration techniques, it allows
smaller area and lower power consumption. The A/D converter occupies a
die area of 2.43 mm2 (1800 μm*1350 μm) and dissipates
118 mW at a 10 MHz clock rate with a 3.3 V single supply voltage in
measurement results. Typical differential nonlinearity (DNL) and
integral nonlinearity (INL) are ±0.73 LSB and ±1.55 LSB,

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35 μm CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection, together with a low-jitter clock circuit, guaranteeing the high dynamic performance for the ADC. A scheme of capacitor-switching and a symmetrical layout technique minimizes capacitor mismatch, ensuring the overall linearity. The measured results show that the calibration-free ADC achieves an effective number of bits of 11.6-bit, spurious free dynamic range (SFDR) of 84.8 dB, signal-to-noise-and-distortion ratio (SNDR) of 72 dB, differential nonlinearity of +0.63/−0.6 LSB and integrated nonlinearity of +1.3/−0.9 LSB at 36.7 MHz input and maintains over 75 dB SFDR and 59 dB SNDR up to 200 MHz.
    Journal of Semiconductors 02/2012; 33(2):025012.
  • [Show abstract] [Hide abstract]
    ABSTRACT: We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-mum CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600times and to accurately program a desired offset with maximum observed residual offset of 469 muV and standard deviation of 199 mu V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2008; · 2.24 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A 14b 70MS/s 3-stage pipeline ADC in a 0.13mum CMOS process employs signal insensitive 3D fully symmetric capacitors for high matching accuracy without any calibration scheme. The prototype ADC with a 0.35mum minimum channel length for 2.5V system applications shows measured differential and integral nonlinearities of 0.65LSB and 1.80LSB at 14b, occupies a die area of 3.3mm<sup>2</sup>, and consumes 235mW at 70MS/s
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006