Conference Paper

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications

Toshiba Corp., Kawasaki
DOI: 10.1109/ISCAS.2000.856290 Conference: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 2
Source: IEEE Xplore

ABSTRACT A scalable MPEG-4 video codec architecture is proposed to achieve
low power consumption and high cost-effectiveness for IMT-2000
multimedia applications. The MPEG-4 video codec consists of a 16-bit
multimedia-extended RISC processor and dedicated hardware accelerators,
which bring about both low power consumption and programmability. The
proposed architecture is extended and applied for the development of two
MPEG-4 LSIs. One is an MPEG-4 video codec LSI, which performs an MPEG-4
video encoding and decoding at 15 frames per second with quarter common
intermediate format. The other is an MPEG-4 audiovisual LSI, containing
three 16-bit RISC processors and a 16-Mbit embedded DRAM, executes the
major functions of 3GPP 3G-324M video telephony for IMT-2000
applications. By introducing the optimization of the embedded DRAM
configuration, clock gating technique, and low power motion estimation,
the MPEG-4 audiovisual LSI consumes only 240 mW when it activates MPEG-4
video SP@L1 codec, the AMR speech codec, and the H.223 annex B multiplex
at 60 MHz clock rate

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