A novel 6.4 μm2 full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 μm-generation CMOS technology
ABSTRACT Summary form only given. A unique 6.4 μm2 6Tr. SRAM
cell has been developed using an advanced CMOS technology implemented in
0.25 μm design rule for high density and high speed applications.
Very small aspect ratio of 0.63 has been achieved for the cell design.
Special features in the layout are parallel active regions and
orthogonal gate electrodes, all bar shape. Stable cell operation has
been obtained at 0.5 V
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ABSTRACT: Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. The cells reside in a low leakage, voltage collapsed, low standby power mode when not being accessed. Both six transistor and seven transistor variations of the basic approach are explored through simulation and measured results. The circuit topology, layout, and impact on memory design of the proposed cell designs are described. Measured results on a 130 nm foundry fabrication process demonstrate the viability of three of the possible cell configurations. Circuit simulation is used to explore the cell stability in the presence of process variations, and to show the value of the proposed SRAM cell designs on future scaled manufacturing technologies.Journal of Computers. 01/2008;
Conference Paper: Design of SRAM with sleep transistor for leakage reduction[Show abstract] [Hide abstract]
ABSTRACT: CMOS technology continues to drive the reduction in switching delay and power while improving area density. However, the transistor miniaturization also introduces many new challenges in Very Large Scale Integrated (VLSI) circuit design, such as sensitivity to process variations and increasing transistor leakage. On the other hand, the need for on chip memory in Digital systems has been increasing day by day to make the equipment faster as well as portable.Electronic Design, 2008. ICED 2008. International Conference on; 01/2009
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ABSTRACT: Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. The cell circuit topology, layout, and impact on memory design are described. Simulation of operation on 130 and 90 nm technologies and with predictive technology models for 65 and 45 nm technologies demonstrate the leakage reduction and measurement on 130 nm demonstrates improved read stability20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India; 01/2007