Conference Paper

A scalable cache coherent architecture for large-scalemesh-connected multiprocessors

Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon;
DOI: 10.1109/ISPAN.1997.645056 Conference: Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97) Proceedings., Third International Symposium on
Source: IEEE Xplore

ABSTRACT Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data, however, most protocols suffer from extraneous cache invalidates or updates due to insufficient pointers. We focus on large-scale mesh-connected multiprocessors built on top of wormhole and dimension ordered routing networks. In such networks, worms are major bricks for communications, which transit all the intermediate nodes on their way to a destination. From such an observation, we propose a new directory-based protocol DirQ with limited pointers, which can represent either one node or a set of nodes when being widely shared. For √N×√N processors system, our protocol needs Θ(N3/2 log N) bits for directory memory which is much more scalable compared to the full-map protocol. In terms of latency and traffic volume for cache coherence, our analytic models show that DirQ outperforms other limited protocols, and further comparable to the full-map one

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