Conference Proceeding

A design framework for hybrid-access caches

Sch. of Comput. Sci., McGill Univ., Montreal, Que.
02/1995; DOI:10.1109/HPCA.1995.386547 ISBN: 0-8186-6445-2 pp.144 - 153 In proceeding of: High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on
Source: IEEE Xplore

ABSTRACT High-speed microprocessors need fast on-chip caches in order to
keep busy. Direct-mapped caches have better access times than
set-associative caches, but poorer miss rates. This has led to several
hybrid on-chip caches combining the speed of direct-mapped caches with
the hit rates of associative caches. In this paper, we unify these
hybrids within a single framework which we call the hybrid access cache
(HAC) model. Existing hybrid caches lie near the edges of the HAC design
space, leaving the middle untouched. We study a group of caches in this
middle region, a group we call half-and-half caches, which are half
direct-mapped and half set-associative. Simulations confirm the
predictive valve of the HAC model, and demonstrate that, for medium to
large caches, this middle region yields more efficient cache designs

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Keywords

associative caches
 
caches
 
Direct-mapped caches
 
efficient cache designs
 
Existing hybrid caches
 
fast on-chip caches
 
HAC model
 
High-speed microprocessors
 
hit rates
 
hybrid on-chip caches
 
hybrids
 
large caches
 
middle region
 
middle region yields
 
middle untouched
 
rates
 
set-associative
 
set-associative caches
 
Simulations
 
single framework