Conference Paper

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Samsung Electronics, Kyungki-Do
DOI: 10.1109/VLSIT.1992.200619 Conference: VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Source: IEEE Xplore


Micro villus patterning (MVP) technology which delivers the
maximized cell capacitance is discussed. The key feature of the MVP
technology is the formation of a hemispherical grain (HSG) archipelago
and its transference to the underlayered oxide. The HSG archipelago
pattern is produced on the oxide layer, and, by using that pattern as an
etch mask, the oxide archipelago pattern is again transferred to the
storage poly for the formation of villus bars by anisotropic dry etch.
After the etching process, the oxide etch mask pattern is stripped away
by using oxide wet etchant, so that additional Fin undercut structure is
achieved underneath the main body. The main body of the storage
electrode can be formed by single deposition and etch process, so that
the storage electrode structure is strong enough to maintain its
physical stability in spite of the complication of its shape. A 256-Mb
DRAM-cell size of 0.6~0.8 μm2 having more than 30 fF of
cell capacitance with a stack structure, has been realized

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