Conference Paper

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Samsung Electronics, Kyungki-Do
DOI: 10.1109/VLSIT.1992.200619 Conference: VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Source: IEEE Xplore

ABSTRACT Micro villus patterning (MVP) technology which delivers the
maximized cell capacitance is discussed. The key feature of the MVP
technology is the formation of a hemispherical grain (HSG) archipelago
and its transference to the underlayered oxide. The HSG archipelago
pattern is produced on the oxide layer, and, by using that pattern as an
etch mask, the oxide archipelago pattern is again transferred to the
storage poly for the formation of villus bars by anisotropic dry etch.
After the etching process, the oxide etch mask pattern is stripped away
by using oxide wet etchant, so that additional Fin undercut structure is
achieved underneath the main body. The main body of the storage
electrode can be formed by single deposition and etch process, so that
the storage electrode structure is strong enough to maintain its
physical stability in spite of the complication of its shape. A 256-Mb
DRAM-cell size of 0.6~0.8 μm2 having more than 30 fF of
cell capacitance with a stack structure, has been realized

0 Bookmarks
 · 
49 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd STrap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605μm<sup>2</sup> at 0.25 μm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells. The BEST cell concept, process, and design, as well as preliminary results obtained from a 256 Mb DRAM development test chip, processed with optical lithography down to 0.25 μm design rules, are presented in this paper
    Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International; 01/1994
  • [Show abstract] [Hide abstract]
    ABSTRACT: High-reliability and good-performance stacked storage capacitors with high capacitance value of 17.8 fF/μm<sup>2</sup> has been realized using low-pressure-oxidized thin nitride films deposited on roughened poly-Si electrodes. These novel electrodes are fabricated by H <sub>3</sub>PO<sub>4</sub>-etching and are RCA-cleaned. The leakage current density at +2.5 and -2.5 V are 0.07×10<sup>-9</sup> and -2.4×10<sup>-8</sup> A/cm<sup>2</sup>, respectively, fulfilling the requirements of 256 Mb DRAM's. Weibull plots of time-dependent-dielectric-breakdown (TDDB) characteristics under constant current stress and constant voltage stress also show tight distribution and good electrical properties. Hence, this easy and simple technique is promising for future high-density DRAM's applications
    IEEE Electron Device Letters 10/1998; · 2.79 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Due to new memory-cell architectures, the leakage-current requirements for semiconductor memories will become less stringent with increased levels of integration. The implication of these requirements with regard to allowable metallic contamination levels is investigated with a one-dimensional model based on Shockley-Read-Hall generation-recombination. The model was developed to predict leakage-current in carrier-depleted regions as a function of basic process and metallic contaminant parameters. As device dimensions are reduced, transition metal homogeneous contamination in process chemicals can be an important source of generation-recombination centers that result in the dominant generation-current in the space-charge region. The model allows an estimation of an upper bound for transition metal contamination in advanced processes and is applied for DRAM leakage predictions. Using the model, it is demonstrated that the trend toward lower leakage-current density requirements reverses after the 64-Mbit generation DRAM as a result of memory-cell architecture trends which significantly reduce the space-charge volume
    Advanced Semiconductor Manufacturing Conference and Workshop. 1994. ASMC 94 Proceedings. IEEE/SEMI; 12/1994