Article
Algorithm for Formation of Loop Admittance Matrix
West Virginia University
IEEE Transactions on Power Apparatus and Systems 10/1972; PAS91(5):1743  1749. DOI: 10.1109/TPAS.1972.293495 Source: IEEE Xplore
ABSTRACT
This paper derives the algorithm for building the loop admittance matrix. The algorithm is found by obtaining the dual of the algorithm for the formation of the bus impedance matrix. An application of the algorithm is presented.

 "[8] suggests a method to measure the admittance matrix for a typical antenna array. An algorithm for building the loop admittance matrix is presented in [9] which is based on a bus impedance matrix. The concept of building an infinite admittance matrix is utilized in [10] in order to present new analysis of switchedcapacitor networks. "
Conference Paper: A general algorithm to automatically create admittance matrices for electric networks
[Show abstract] [Hide abstract]
ABSTRACT: In this paper, a general method to automatically create admittance matrices for power electric networks is presented. This is a part of a joint project between Mississippi State University and University of Texas at Austin Center for Electromechanics (CEM). Starting with an electric network designed in the Mathworks software Simulink (SimPowerSystems) and output from Simulink as an XML file, we parse the XML file for the relevant information (blocks, connectivity, and parameters). The underlying algorithm consists of four stages: 1) Calculate the conductance values of the components in each block, 2) Build a matrix representing the connectivity of components, 3) Assign a unique number for each node, and finally 4) Calculate the admittance matrix using the data obtained from the previous steps. This is the initial work to support the development of a parallel computing tool where the power system will be solved using a tool developed by the University of Texas called CEMSolver. The second phase of this joint project will be finding the most optimal partitioned systems in such a way that the matrices of each partition are distributed to different CPUs and the total CPU usage for these subsystems will be minimal. Thus, the power system will be partitioned and each partition will have its own admittance matrix.Electric Ship Technologies Symposium (ESTS), 2013 IEEE; 01/2013
Similar Publications
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.