Using stacked bitlines and hybrid ROM cells to form ROM and SRAM-ROM with increased storage density

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Impact Factor: 2.4). 01/2007; 53(12):2595 - 2605. DOI: 10.1109/TCSI.2006.885995
Source: IEEE Xplore


ROM cell architectures are proposed that have roughly 20% greater storage density in the cell array compared to that of a conventional ROM. Increased density is achieved by exploiting the multiple interconnect layers now available in common logic processes and by using multiple ROM cell types in combination. The storage density of arrays of these hybrid ROM cells increases further as more interconnect layers become available. In addition, a new SRAM-ROM architecture is presented that capitalizes on these techniques to add ROM capability to a conventional SRAM cell with no additional transistors in the memory cell and little or, in some cases, no impact on the cell area

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