Article

Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Impact Factor: 2.24). 01/2007; DOI: 10.1109/TCSI.2006.885995
Source: IEEE Xplore

ABSTRACT ROM cell architectures are proposed that have roughly 20% greater storage density in the cell array compared to that of a conventional ROM. Increased density is achieved by exploiting the multiple interconnect layers now available in common logic processes and by using multiple ROM cell types in combination. The storage density of arrays of these hybrid ROM cells increases further as more interconnect layers become available. In addition, a new SRAM-ROM architecture is presented that capitalizes on these techniques to add ROM capability to a conventional SRAM cell with no additional transistors in the memory cell and little or, in some cases, no impact on the cell area

0 Bookmarks
 · 
45 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: There are many important applications, such as math function evaluation, digital signal processing, and built-in self-test, whose implementations can be faster and simpler if we can have large on-chip “tables” stored as read-only memories (ROMs). We show that conventional de facto standard 6T and 8T static random access memory (SRAM) bit cells can embed ROM data without area overhead or performance degradation on the bit cells. Just by adding an extra wordline (WL) and connecting the WL to selected access transistor of the bit cell (based on whether a 0 or 1 is to be stored as ROM data in that location), the bit cell can work both in the SRAM mode and in the ROM mode. In the proposed ROM-embedded SRAM, during SRAM operations, ROM data is not available. To retrieve the ROM data, special write steps associated with proper via connections load ROM data into the SRAM array. The ROM data is read by conventional load instruction with unique virtual address space assigned to the data. This allows the ROM-embedded cache (R-cache) to bypass tag arrays and translation look-aside buffers, leading to fast ROM operations. We show example applications to illustrate how the R-cache can lead to low-cost logic testing and faster evaluation of mathematical functions.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(9):1583-1595. · 1.22 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents memory-based embedded digital ATE (Automatic Test Equipment) - a new logic BIST methodology that can deliver deterministic test stimuli and stores output responses on a chip. The proposed scheme consists of test data compression logic and a new on-chip SRAM structure, which is operated as a ROM when the logic BIST mode is on. The new BIST-oriented RAM (BRAM) implements ROM features in the BIST mode and incurs no performance penalty in the normal SRAM mode of operation. BRAM can be designed by inserting an additional word line in a row to a conventional SRAM bit-cell (no increase in bit-cell area). BRAM stores the compressed test vectors that can be transmitted to on-chip decompressors during test mode. BRAM also accepts compacted output responses. Experimental results show that BRAM performs stable and high-performance ROM operations in the BIST mode. Run-length coding can be incorporated into the proposed test data compression to reduce test data volume further. Test data volume and fault coverage on ISCAS89 benchmark show that the proposed test methodology can be used as a stand-alone BIST scheme while providing test quality of deterministic tests.
    VLSI Test Symposium (VTS), 2011 IEEE 29th; 06/2011