A Cochlear-Implant Processor for Encoding Music and Lowering Stimulation Power

Adv. Bionics, Sylmar
IEEE Pervasive Computing (Impact Factor: 1.55). 02/2008; 7(1):40-48. DOI: 10.1109/MPRV.2008.3
Source: IEEE Xplore


Cochlear implants (CIs), or bionic ears, restore hearing in profoundly deaf (greater than -90 dB hearing loss) patients. They function by transforming frequency patterns in sound into corresponding spatial electrode-stimulation patterns for the auditory nerve. Over the past 20 years, improvements in sound-processing strategies, in the number of electrodes and channels, and in the rate of stimulation have yielded improved sentence and word recognition scores in patients. Next- generation implants will be fully implanted inside the patient's body. Consequently, power consumption requirements for signal processing will be very stringent.

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    • "The proposed sensor builds on a long history of development [15]–[17] by addressing a number of shortcomings of previous work. Previous AER silicon cochlea designs offer either only monaural operation [5]–[7], [35], poor channel matching [5], [10], [18], do not integrate biasing circuits for process, voltage, and temperature tolerant biasing [5], [15], [18], do not integrate microphone preamplifiers [5], [7], [8], [10], [18], or do not include any per-channel calibration capability [5], [8], [10], [18]. None of the prior work has open-sourced host software APIs and algorithms which enable rapid development of application scenarios [19]. "
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    ABSTRACT: This paper proposes an integrated event-based binaural silicon cochlea system aimed at efficient spatial audition and auditory scene analysis. The cochlea chip has a matched pair of digitally-calibrated 64-stage cascaded analog second-order filter banks with 512 pulse-frequency modulated (PFM) address-event representation (AER) outputs. The quality factors (Qs) of channels are individually adjusted by local DACs. The 2P4M 0.35 um CMOS chip consumes an average power of 14 mW including its integrated microphone preamplifiers and biasing circuits. Typical speech data rates are 10 k to 100 k events per second (eps) with peak output rates of 10 Meps. The event timing jitter is 2 us for a 250 mVpp input. It is shown that the computational cost of an event-driven source localization application can be up to 40 times lower when compared to a conventional cross-correlation approach.
    IEEE Transactions on Biomedical Circuits and Systems 08/2014; 8(4):453-464. DOI:10.1109/TBCAS.2013.2281834 · 2.48 Impact Factor
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    • "This architecture implementation is similar in some ways to the adiabatic circuits used to reduce power in digital design [12], [13]. Our scheme can also be combined with algorithmic strategies to reduce power [14], [15]. This architecture minimizes the power lost in driving the electrodes in our wireless-implanted stimulator. "
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    ABSTRACT: This paper presents a power-efficient neural stimulator integrated circuit, designed to take advantage of our understanding of iridium-oxide electrode impedance. It efficiently creates a programmable set of voltage supplies directly from a secondary power telemetry coil, then switches the target electrode sequentially through the voltage steps. This sequence of voltages mimics the voltage of the electrode under the constant current drive, resulting in approximately constant current without the voltage drop of the more commonly used linear current source. This method sacrifices some precision, but drastically reduces the series losses seen in traditional current sources and attains power savings of 53%-66% compared to these designs. The proof-of-concept circuit consumes 125 μW per electrode and was fabricated in a 1.5-μm CMOS process, in a die area of 4.76 mm(2).
    IEEE Transactions on Biomedical Circuits and Systems 02/2011; 5(1):20-29. DOI:10.1109/TBCAS.2010.2076384 · 2.48 Impact Factor
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    • "ILICON (Si) cochleae emulate cochlear processing of sound stimuli in very-large scale integrated (VLSI) systems , attempting to match the biological cochlea's sound sensitivity, frequency selectivity, and dynamic range. The effort to build artificial cochleae in Si has been largely motivated by their potential applications in hearing aids, cochlear implants, and other portable devices that demand real-time, low-power signal processing for speech recognition; these requirements favor subthreshold analog VLSI designs [1]. Furthermore, analog VLSI is amenable to cochlea-like distributed processing due to its compact computational elements, large numbers of which can be integrated in a small area of Si. "
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    ABSTRACT: We present a mixed-signal very-large-scale-integrated chip that emulates nonlinear active cochlear signal processing. Modeling the cochlea's micromechanics, including outer hair cell (OHC) electromotility, this silicon (Si) cochlea features active coupling between neighboring basilar membrane (BM) segments-a first. Neighboring BM segments, each implemented as a class AB log-domain second-order section, exchange currents representing OHC forces. This novel active-coupling architecture overcomes the major shortcomings of existing cascade and parallel filter-bank architectures, while achieving the highest number of digital outputs in an Si cochlea to date. An active-coupling architecture Si cochlea with 360 frequency channels and 2160 pulse-stream outputs occupies 10.9 mm<sup>2</sup> in a five-metal 1-poly 0.25-mum CMOS process. The chip's responses resemble that of a living cochlea's: Frequency responses become larger and more sharply tuned when active coupling is turned on. For instance, gain increases by 18 dB and Q <sub>10</sub> increases from 0.45 to 1.14. This enhancement decreases with increasing input intensity, realizing frequency-selective automatic gain control. Further work is required to improve performance by reducing large variations from tap to tap.
    IEEE Transactions on Biomedical Circuits and Systems 01/2010; 3(6-3):444 - 455. DOI:10.1109/TBCAS.2009.2027127 · 2.48 Impact Factor
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