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S-Parameters Characterization of Through,

Blind, and Buried Via Holes

Giulio Antonini, Member, IEEE, Antonio Ciccomancini Scogna, Member, IEEE, and

Antonio Orlandi, Senior Member, IEEE

Abstract—A method for de-embedding the scattering parameters matrix for single-end or differential through, buried, and blind via

holes in multilayer printed circuit board for high-speed digital applications is presented. The proposed technique starts from a

measurement or simulation of the structure containing the discontinuity and, after the structure’s partitioning, extracts the scattering

parameters of the required discontinuity. The procedure is applied to different kinds of single-ended and differential via holes and is

validated by measurements. The Finite Integration Technique is used to perform the needed three-dimensional electromagnetic

simulations. Due to its reduced CPU time, the proposed methodology is suitable for a parametric analysis on the electrical performance

of the via holes discontinuities and it gives useful results for the extraction of accurate computer-aided design models.

Index Terms—Signal integrity, de-embedding technique, buried, blind, and through via holes.

?

1

T

local-area networks (WLANs), support different applica-

tions, but share a common denominator: to bring users

higher speed and computing performances and smaller

dimensions with less weight.

The first condition requires, at the hardware level,

systems working with digital signals at bitrates between a

few megabits per second up to 54 Mbps as the emerging

IEEE 802.11 physical layer (PHY) 802.11a PHY extends the

classic 2.4 GHz band into the 5 GHz band. If dynamical link

adaptation protocols are implemented, then the same

system should be adequate for almost the entire range of

bitrate. The last condition requires the development and

implementation of low power consumption devices that, in

turn, call for ever-decreasing signal levels and higher

signal-to-noise ratio. To meet these requirements, the

hardware engineer must consider and minimize all the

factors that impact the integrity of the digital signals in

order to ensure the correct system functioning. Among

those factors, the on-chip and on-board discontinuities of

the high-speed interconnections have a major role, hence

the correct characterization of discontinuities is a manda-

tory task for a meaningful signal integrity (SI) analysis. The

layout of printed circuit boards (PCB) [1] involves a large

number of discontinuities such as connectors, unusual

terminations, bends, presence of packages, via holes, line

crossing, etc. Their presence can cause signal distortion and

the associated raising of common mode voltage and current

components. The spoiling of the signal quality has a direct

INTRODUCTION

HE modern mobile systems, ranging from Third Gen-

eration (3G) cellular phones to the terminals of wireless

impact on the functionality of the mounted digital devices.

The common mode components are usually small in

magnitude and their effects on the signal quality minor.

However, this small amount of common mode current can

significantly increase the level of electromagnetic interfer-

ences (EMI), degrading the system performances from an

electromagnetic compatibility (EMC) point of view. The

understanding of the physical phenomena, occurring on-

board for the presence of discontinuities, responsible for

common mode creation (or conversion) directly helps the

understanding of the physics and of the source of radiation,

allowing the designer to anticipate EMI by using SI

information.

Because of this, the evaluation of the electrical perfor-

mances of the discontinuities and their impact on the

signals is an essential step at the design stage of a board.

Furthermore, the evaluation of the electric performances of

the discontinuities allows one to extract equivalent circuit

models [2], [3] that can be included as part of more complex

circuits representing the board. Circuit simulators are then

relatively fast and predict signals accurately. From these SI

quantities, it is possible to anticipate a board’s related EMI.

The evaluation of discontinuity’s performances, conveni-

ently done in terms of scattering parameters (S-parameters),

can be done by means of numerical simulations or by

measurements. The numerical simulations must capture the

correct distribution of the em field in order to take into

account all the significant effects due to the discontinuity; in

the frequency range of operations for these digital systems

(up to several gigahertz), this means a high level of detail in

the description of the geometry along with its high aspect

ratio call for significant requirements of CPU time and

memory. On the other hand, from a measurement point of

view, at the frequencies of interest here, it is generally not

possible to gain access to the structure without impacting

the measurement being made. An example among all is the

experimental characterization of a via hole in which the

presence of feeding parts (traces, adapters, or pads)

174IEEE TRANSACTIONS ON MOBILE COMPUTING, VOL. 2,NO. 2, APRIL-JUNE 2003

. The authors are with the UAq EMC Laboratory, Department of Electrical

Engineering, University of L’Aquila, I-67040, Poggio di Roio, L’Aquila,

Italy. E-mail: {antonini, scogna, orlandi}@ing.univaq.it.

Manuscript received 30 Jan. 2003; revised 26 Apr. 2003; accepted 29 Apr.

2003.

For information on obtaining reprints of this article, please send e-mail to:

tmc@computer.org, and reference IEEECS Log Number 0007-0103.

1536-1233/03/$17.00 ? 2003 IEEE Published by the IEEE CS, CASS, ComSoc, IES, & SPS

Page 2

connecting the instrument’s ports to the via must always be

present. To overcome the above-mentioned difficulties, it

has become standard practice to characterize the effects of

the test access ports, feeding lines, or adapters and then to

separate them from the measurement relative to the

complete structure: The remaining data are those associated

ANTONINI ET AL.: S-PARAMETERS CHARACTERIZATION OF THROUGH, BLIND, AND BURIED VIA HOLES175

Fig. 1. Test configuration: microstrip on a PEC reference plane and its partitioning in three elementary substructures.

Fig. 2. Comparison of S parameters obtained by FIT method, the de-embedding technique, and the de-embedding technique with closed formulas:

(a) jS11j, (b) phase of S11, and (c) jS21j, (d) phase of S21.

Page 3

to the electric behavior of the part (discontinuity) of interest.

This procedure is known as de-embedding [4], [5], [6]. In

recent years, a number of de-embedding methods have

been reported in the literature and their references give

useful hints for modeling [7], [8], [9], [10] and measure-

ments [11], [12], [13], [14].

The proposed approach starts from the knowledge (by

measurements or simulation) of the S parameters of a

structure (named in the following a “complete structure”)

containing the discontinuity to be studied and other

auxiliary parts such as traces, adapters, etc. The S para-

meters of these parts are evaluated by means of numerical

methods or, as will be shown in the paper, by analytical

formulation. Finally, the S matrix of the discontinuity is

extracted from the S matrix of the complete structure by

means of the information on the auxiliary parts.

This paper applies the above mentioned procedure to on-

board discontinuities as via holes (vias) in multilayer PCB.

Thepaperisorganizedasinthefollowing:InSection2,the

de-embedding procedure is illustrated showing its possibi-

lities and limitations. In Section 3, the S parameters of four

different kinds of via are evaluated by de-embedding; all the

176IEEE TRANSACTIONS ON MOBILE COMPUTING, VOL. 2,NO. 2,APRIL-JUNE 2003

Fig. 3. Test board’s configuration: (a) top view and (b) side view.

Fig. 4. Comparison among computed and measured S-parameters: (a) jS11j, (b) phase of S11, (c) jS21j, and (d) phase of S21.

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neededthree-dimensional (3D)simulationsarecarriedon by

the Finite Integration Technique (FIT) [15]. Section 4 offers

some conclusions.

2THE DE-EMBEDDING TECHNIQUE

To illustrate the developed de-embedding technique, the

simple case of a trace whose length is l = 90 mm, on a

perfect electric conductor (PEC), a finite plane is considered.

The relevant dimensions and geometry are in Fig. 1.

tep is the evaluation (measurement or simulation) of the

scattering matrix Stot (bold letters refer to matrices or

vectors) between the terminals ports 1 and 2 of the complete

structure. Then, the structure is partitioned [16] in three

substructures assumed electromagnetically decoupled

among each other. The task of the de-embedding is the

evaluation of the S2matrix of the central parts. The S1and

S3 matrices of the corresponding substructures are com-

puted by the FIT method.

In oo allow a correct matrix manipulation, the scattering

matrices must be transformed in the transfer scattering

matrices T by means of standard S-to-T transformations

[17]. After the transformations

Stot? !Ttot

S1? !T1

S3? !T3;

ð1Þ

one can write

Ttot¼ T1T2T3

ð2aÞ

and, hence,

T2¼ T?1

1TtotT?1

3:

ð2bÞ

The last step is the back transformation T2! S2via the T-

to-S conversion formulas [17].

In Fig. 2, there is a comparison between the magnitude

and phase of the frequency spectra of S11 and S21 of the

central part of the structure in Fig. 1, evaluated by means of

the FIT method and by the de-embedding technique.

This procedure requires at least two 3D simulations for

the evaluation of the matrices S1 and S3 representing the

parts of the partitioned structure in which one is not

interested. It turns out that, when these parts of the

structure have canonical geometries such as microstrips or

striplines, then their S matrices can be evaluated by means

of closed form formulas giving a consistent computational

time saving.

In particular, for the simple case in Fig. 1, from the

knowledge of the characteristic impedance Z0and effective

dielectric permettivity "effgiven by [18]

ffiffiffiffiffi

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

w

one can evaluate the propagation coefficient ? and then the

ABCD matrix; from the ABCD matrix, the S parameters are

Z0¼

?0

ffiffiffiffiffiffiffiffiffi

p

p

2?"e"0

ln

8h

wþw

4h

??

;

ð3aÞ

"eff¼"rþ1

2

þ"r?1

2

1 þ10h

r

? 0:217 "r? 1

ðÞ

tffiffiffiffiffiffiffi

wh

p

;

ð3bÞ

easily calculated. Fig. 2 also report the S parameters for the

central part of the microstrip in Fig. 1 evaluated by the de-

embedding procedure by using the closed form formulation

for Sections 1 and 3. The overall agreement of magnitudes

and phases is satisfactory.

3VIA HOLE CHARACTERIZATION

The above described de-embedding technique is applied to

extract the S parameters of different kinds of via holes

discontinuities. Depending on their terminations to the

reference plane, they are indicated as single-end or

differential; depending on their vertical cross section

throughout the board’s stack up, they are called through

hole, buried, or blind vias.

3.1

A single-end through hole via connecting two 50 mm long

microstrips laying on the opposite sides of a four layers

board is presented in Fig. 3 with its relevant dimensions.

The through hole via is a vertical connection through the

board that goes from the top to the bottom layer

independently by the position of the signal’s layers that

must be connected. Fig. 4 shows the measured and FIT

computed S-parameters for the complete structure.

The structure is then partitioned into three substructures,

as shown in Fig. 5 and S1and S2of the isolated microstrips 1

and 2 in Figs. 5a and 5c are calculated by the FIT technique.

Single-End, Through Hole Via

ANTONINI ET AL.: S-PARAMETERS CHARACTERIZATION OF THROUGH, BLIND, AND BURIED VIA HOLES177

Fig. 5. Partitioned structure: (a) microstrip 1, (b) via, and (c) microstrip 2.

Page 5

By applying (1) and (2), the scattering matrix S3of the via

structure in Fig. 5b is computed. The presence of the two

stubs,each10mmlong,isneededtoallowthedecayingofthe

higherordermodesduetothediscontinuityintroducedbyof

the lumped exciting ports at the terminations of the traces.

Fig.6comparesthescatteringparametersfortheviastructure

in Fig. 5b evaluated by a direct 3D FIT simulation, by the

proposed de-embedding technique and by an integral

method [19].

3.2Single-Ended, Blind Via

Blind vias are vertical structures that go from the outer

layers to an internal one without passing through all the

vertical stack up. The side view of a blind via is shown in

Fig. 7. The partitioning (see Figs. 7b, 7c, and 7d) and the de-

embedding technique to obtain the S parameters for the

structure in Fig. 7c are applied at this structure.

These S parameters are reported in Fig. 8 where they

are compared with those evaluated by a computational

intensive 3D simulation. From the knowledge of S21, one

can also compute the eye pattern [20]. This time domain

representation of the results complete the information

obtained by the frequency domain analysis of the

S-parameters. The comparison of the eye pattern of the

complete structure (Fig. 9a) with that of the only de-

embedded via structure (Fig. 9b) allows one to quantify

the percentage of jitter and eye opening subtracted from

the total design budget, by the considered discontinuity.

The eventual presence of impedance mismatches shown

in the form of an eye pattern ringing indicates the

possible hazard for radiated emissions at frequencies

multiple of the ringing frequency.

3.3Differential, Through Hole Via

High-speed digital signals are carried by differential

traces. Fig. 10a shows the top view of a differential pair

going through several layers by means of a pair of vias

[21]. Two vias configurations are considered: a through

hole in Fig. 10b and a buried via in Fig. 10c. A buried

178 IEEE TRANSACTIONS ON MOBILE COMPUTING, VOL. 2, NO. 2,APRIL-JUNE 2003

Fig. 6. Magnitude and phase of (a) and (b) S11 and (c) and (d) S21 evaluated by FIT technique, de-embedding technique, and integral method

(CEMPIE).

Page 6

via is a direct connection between two signal layers

without emerging at any of the outer layers. For

applying the proposed procedure to a differential trace,

four independent ports are considered, the structure is

partitioned as in Fig. 11, and the S3 matrix for the part

in Fig. 10b is obtained.

If one is interested in the performances of this structure

at a differential mode propagation, the introduction of a

mixed mode scattering matrix Smm[22], [23] is needed. It

can be obtained by the 4 x 4S3by

Smm¼ MS3M?1¼

Sdd

Scd

Sdc

Scc

??

;

ð4Þ

where

M ¼

1ffiffiffi

2

p

1

0

1

0

?1

0

1

0

0

1

0

1

0

?1

0

1

0

B

B

@

1

C

C

A:

ð5Þ

Submatrix Sddis in the form

ANTONINI ET AL.: S-PARAMETERS CHARACTERIZATION OF THROUGH, BLIND, AND BURIED VIA HOLES 179

Fig. 7. Cross section of a single-ended blind via hole: (a) complete structure and partitioned structures, (b) microstrip, (c) blind via, and (d) stripline.

Page 7

Sdd¼

Sdd11

Sdd21

Sdd12

Sdd22

??

:

ð6Þ

The magnitude of the S parameters Sdd11 and Sdd21

computed by a complete 3D FIT simulation or by the de-

embedding technique are in Fig. 12 along with the

computed eye pattern in Fig. 13 for the differential signal

3.4

For this kind of via, whose side view is shown in Fig. 10c,

the computed S parameters are in Fig. 14. One can notice

that, although the length of the differential vias is the same

in Fig. 10b and 10c, the reflections introduced by the buried

are less than those introduced by the through hole. In fact,

the two parts of unused via above signal’s layer S3 and

below signal’s layer S4 act as a load on the via amplifying

the mismatching with the corresponding traces.

Differential, Buried Via

4CONCLUSION

Ade-embeddingtechniquehasbeenproposedtoevaluatethe

S parameters of different kinds of via holes discontinuities.

Starting from the measured or numerically computed S

parameters of the complete structure, the procedure allows

one to obtain the S parameters of the isolated vias taking into

account also the eventual presence of small sections of traces

conductors.Inthisway,itispossibletoobtainacharacteriza-

tion of the via structure that would be impossible to have by

means of direct measurements. The validation of the

proposed approach by means of comparisons with measure-

ments and numerical simulations performed with different

and independent methods has shown the reliability of the

procedureandoftheresultsintermsofSparameters.Thiscan

be considered a solid base for circuit modeling of these

discontinuities.

ACKNOWLEDGMENTS

The authors wish to thank Professor J. Drewniak, Ing. G.

Selli, and Mr. S. Luan in the UMR EMC Laboratory at the

University of Missouri-Rolla for making available the

measured results and the CEMPIE simulations.

180IEEE TRANSACTIONS ON MOBILE COMPUTING,VOL. 2, NO. 2, APRIL-JUNE 2003

Fig. 8. Magnitude of (a) S11and (b) S21evaluated by FIT technique and the de-embedding technique.

Fig. 9. Eye pattern of a 2.5 Gb/s signal for (a) the complete structure and (b) the via structure.

Page 8

ANTONINI ET AL.: S-PARAMETERS CHARACTERIZATION OF THROUGH, BLIND, AND BURIED VIA HOLES 181

Fig. 10. Differential traces and vias: (a) top view and A-A section, (b) through hole via, and (c) buried via.

Fig. 11. Partitioned structure: (a), (c) differential striplines, and (b) differential vias.

Page 9

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Fig. 12. Magnitude of (a) Sdd11and (b) Sdd21evaluated by FIT technique and the de-embedding technique.

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Page 10

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106, Jan. 1999.

Giulio Antonini (M’94) received the Laurea

degree (summa cum laude) in electrical engi-

neering in 1994 from the University of L’Aquila

and the PhD degree in electrical engineering in

1998 from the University of Rome “La Sapien-

za.” Since 1998, he has been with the UAq EMC

Laboratory, Department of Electrical Engineer-

ing at the University of L’Aquila where he is

actually a tenured assistant professor. His

research interests focuses on EMC analysis,

numerical modeling, and in the field of signal integrity for high-speed

digital systems. In 1998, he received the Best Transactions Paper

Award for the best paper published in the IEEE Transactions on

Electromagnetic Compatibility in 1997. Since 1998, he collaborates with

the IBM T.J. Watson Research Center, New York, in the developments

of algorithms for PEEC modeling. Dr. Antonini is a member of the IEEE

EMC TC-9 Committee. He is a member of the IEEE.

ANTONINI ET AL.: S-PARAMETERS CHARACTERIZATION OF THROUGH, BLIND, AND BURIED VIA HOLES183

Fig. 14. Magnitude and phase of (a) and (b) Sdd11and (c) and (d) Sdd21evaluated by FIT technique and the de-embedding technique.

Page 11

Antonio Ciccomancini Scogna received the

Laurea degree in electrical engineering from the

University of L’Aquila in 2001. He is currently a

PhD student in the UAq EMC Laboratory,

Department of Electrical Engineering at the

University of L’Aquila. His research interests

are in the field of EMC numerical modeling and

signal integrity analysis on high-speed digital

boards. He is a member of the IEEE.

Antonio Orlandi (M’90-SM’97) received the

Laurea degree in electrical engineering from

the University of Rome “La Sapienza,” Italy, in

1988. He was with the Department of Electrical

Engineering, University of Rome “La Sapienza”

from 1988 to 1990. Since 1990, he has been

with the UAq EMC Laboratory, Department of

Electrical Engineering at the University of

L’Aquila where he is currently a full professor.

He has authored more than 100 technical

papers which have been published in the field of electromagnetic

compatibility in lightning protection systems and power drive systems.

His current research interests are in the field of numerical methods and

modeling techniques to approach signal integrity and EMC/EMI issues in

high-speed digital systems. Dr. Orlandi received the IEEE Transactions

on Electromagnetic Compatibility Best Paper Award in 1997. He is

member of the Education, TC-9 Computational Electromagnetics, and

TC-10 Signal Integrity Committees of the IEEE EMC Society, and was

chairman of the “EMC INNOVATION” Technical Committee of the

International Zurich Symposium and Technical Exhibition on EMC. From

1996 to 2000, has was associate editor of the IEEE Transactions on

Electromagnetic Compatibility and now serves as an associate editor of

the IEEE Transactions on Mobile Computing. he is a senior member of

the IEEE.

. For more information on this or any computing topic, please visit

our Digital Library at http://computer.org/publications/dlib.

184IEEE TRANSACTIONS ON MOBILE COMPUTING, VOL. 2,NO. 2, APRIL-JUNE 2003