Compact Modeling of MOSFET Wearout Mechanisms for CircuitReliability Simulation
ABSTRACT The integration density of stateoftheart electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hotcarrier injection, timedependent dielectric breakdown, and negative bias temperature instability) and introduces new acceleratedlifetime and SPICE compact models of these wearout mechanisms. Based on these circuitaging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90nm technology to help designers understand devicefailure behaviors, predict circuit reliability, and improve product robustness.

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Page 1
98IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008
Compact Modeling of MOSFET Wearout
Mechanisms for CircuitReliability Simulation
Xiaojun Li, Member, IEEE, Jin Qin, and Joseph B. Bernstein, Senior Member, IEEE
(Invited Paper)
Abstract—The integration density of stateoftheart electronic
systems is limited by the reliability of the manufactured integrated
circuits at a desired circuit density. Design rules, operating volt
ages, frequencies, and temperatures are precisely chosen to ensure
correct product functional operation over its intended lifetime.
Thus, in order to obtain the overall performance and functionality
bounded by various design and manufacturing constraints, the
integrated circuit reliability must be modeled and analyzed at
the very beginning of design stages. This paper reviews some of
the most important intrinsic wearout mechanisms of MOSFETs
(including hotcarrier injection, timedependent dielectric break
down, and negative bias temperature instability) and introduces
new acceleratedlifetime and SPICE compact models of these
wearout mechanisms. Based on these circuitaging models, a new
SPICE reliability simulation approach is proposed and demon
strated with a simplified SRAM design on a commercial 90nm
technology to help designers understand devicefailure behaviors,
predict circuit reliability, and improve product robustness.
Index Terms—Circuit reliability simulation, device modeling,
hotcarrier (HCI), negative bias temperature instability (NBTI),
reliability modeling, SPICE, timedependent dielectric breakdown
(TDDB), wearout mechanisms.
I. INTRODUCTION
A
modules, etc.) have been extensively used in the stateoftheart
consumer electronic products (for example, iPhone). Reliability
of these advanced VLSI circuits becomes more and more im
portant as both product designers and manufactures relentlessly
pursuetechnologyadvantagesandstretchdevicephysicallimits
tocapitalizetheconsumerelectronicmarket,whichhasrecently
been growing explosively. Competitors in this market would re
lentlessly force any players out of the field if they did not “time
tomarket” their products quickly enough. Even if a player
survived from its competitors, customers would shoot him
down if his products were not “reliable” enough to meet versa
tile applications. “Timetomarket” and “reliability” contradict
DVANCED very large scale integration (VLSI) chips (mi
croprocessors, Flash memories, graphics drivers, wireless
Manuscript received July 6, 2007; revised September 8, 2007.
X. Li is with the Quality and Reliability Engineering, Technology Manu
facturing Group, Intel Corporation, Folsom, CA 95630 USA (email: xiaojun.
m.li@intel.com).
J. Qin and J. B. Bernstein are with the Reliability Engineering, Department
of Mechanical Engineering, University of Maryland, College Park, MD 20740
USA (email: qjin@umd.edu; joey@eng.umd.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TDMR.2008.915629
each other for most of the time, but both are vital for survival
and growth in this market. A possible way to improve reliability
without compromising timetomarket is pushing reliability
characterization and analysis upfront in initial productdesign
stages. As computer techniques become more mature and pow
erful, most aspects of modern chip design have been modeled
and simulated before committing designs to silicon. However,
nowadays, there is a clear gap and roadblock between product
reliability characterization and circuit design. One of the main
reasons for this situation is that there are no effective SPICE
compact models capable of reliability simulation and charac
terization in truly dynamiccircuitsimulation environments.
The engine of any circuitreliability simulation is without
doubt the devicefailure models. However, the advancement of
devicefailure modeling has fallen behind the development of
CMOS technology and raised many new issues related to both
circuit performance and reliability. This result is attributable to
the complexity of MOSFET failure physics and the uncertainty
of failure statistics.
With the scaling of MOSFETs into deepsubmicrometer
regime, negative bias temperature instability (NBTI) is be
coming a resurgent hot topic in the reliability community.
In recent years, NBTI has attracted a lot of research interest
and industry investment toward further understanding of its
degradation physics and circuitlevel impacts. There are many
publications focusing on NBTI mechanism itself, however, at
circuit level, NBTI is convoluted with many other intrinsic
wearout mechanisms. These mechanisms may interact with,
interfere with, or reinforce each other during normal circuit
operations. By introducing a set of acceleratedlifetime and
SPICE compact models of the most important intrinsic wearout
mechanisms in advanced MOSFETs, this paper brings some
new concepts in reliability modeling and tries to integrate
NBTIspecific reliability simulation practice into a broader en
vironment with a holistic method for circuitreliability design.
The wearout mechanisms to be addressed include hotcarrier
injection (HCI), timedependent dielectric breakdown (TDDB),
and NBTI. Based on the new acceleratedlifetime and SPICE
compact models of these wearout mechanisms, a simple but ef
fective SPICE reliability simulation approach is developed and
demonstrated by aging simulations of an SRAM design with
reliability model parameters extrapolated from a commercial
90nm technology to help designers accurately predict circuit
reliability and failure rate from the system point of view.
15304388/$25.00 © 2008 IEEE
Page 2
LI et al.: COMPACT MODELING OF MOSFET WEAROUT MECHANISMS FOR CIRCUITRELIABILITY SIMULATION99
II. HCI LIFETIME AND SPICECIRCUIT MODELING
A. AcceleratedLifetime Model
HCI is the phenomenon that carriers at MOSFET’s drain
end gain sufficient energy to inject into the gate oxide and
cause degradation of some device parameters. Channel carriers
become “hot” as they shoot out from the source of a MOSFET,
accelerate in the channel, and experience impact ionization
near the drain junction due to high lateral electric field [1].
Under favorable conditions, some highenergy electrons and/or
holes produced by the impact ionization are redirected and
accelerated to the interface of oxide and silicon surface. A
few “lucky” carriers overcome the surface energy barrier, in
ject into the oxide, and generate interface states and oxide
charges, which are the main mechanisms for degradation of
some MOSFET parameters such as channel mobility, threshold
voltage, transconductance, and drain saturation current. The
shifts in threshold voltage and transconductance are propor
tional to the average trap density, which in turn is inversely
proportional to the effective channel length [2]. Therefore,
reducing the channel length will exacerbate hotcarrier effect.
For future CMOS technologies, even though the powersupply
voltage will be reduced to 1 V or below, HCI is still a signif
icant reliability concern due to the scaling of devicechannel
lengths [3].
Among the three wearout mechanisms discussed in this
paper, HCI is the most thoroughly investigated one, and quite
a few hotcarrier lifetime models and SPICE failurecircuit
models have been proposed in the past two decades. While
some of the HCI lifetime models are based on the simple
drainvoltageaccelerating law, most other successful lifetime
models characterize HCI effect with peak substrate current for
nMOSFETs and peak gate current for pMOSFETs. These semi
empiricalmodelsarevalidatleastdownto0.25µmtechnology.
In the generations beyond (0.25−0.07 µm), research has shown
that existing lifetime models remain more or less applicable at
low voltages [4]. In order to characterize HCI effects in circuit
environment, many HCI SPICE equivalent models have been
proposed and integrated into reliability simulation tools.
Most HCI lifetime models are based on the “lucky electron”
model, in which the hot carrier stress on an nMOSFET, in terms
of generated interface traps ∆Nit, can be related to the electric
field Emat the drain, the draintosource current Ids, and stress
time t in a simple powerlaw relation [5]
∆Nit= C1
?Ids
Wexp
?
−
Φit,e
qλeEm
?
t
?n
(1)
where W is the channel width, Φit,eis the critical energy for
electrons to create an interface trap (Φit,e= 3.7 eV [6]), λeis
the hotelectron meanfree path (λe= 6.7 nm [7]), and C1is
a process constant. The dynamics of interfacetrap generation
is similar to the rate of thermal oxide growth: at initial stage,
interfacetrap generation rate is reactionlimited; therefore,
Nit(t) ∝ t and n = 1; at later stage, the generation is diffusion
limited, then Nit(t) ∝ t1/2and n = 0.5. The overall process is
the compromised result of these two competing processes, and
as a result, the parameter n falls within the range between 0.5
and 1 [6].
The most important parameter in (1) is the electric field
Em (Em cannot be determined accurately by simple cal
culation). A semiquantitative analytical Em model has been
given in [6]
Em=Vds− Vdsat
?3toxxj
(2)
wheretoxisthegateoxide thickness andxjisthedrainjunction
depth.?3toxxjis the characteristic length which models the
typical values are within
three in?3toxxjderives from the ratio of ?si/?sio2[8].
There are many models for Vdsat; among which, the simplest
one is Vdsat= Vgs− Vt, where Vgsis gatetosource voltage
and Vt is the threshold voltage. For shortchannel devices,
Vdsatis channellength (L)dependent, and the relation is often
modeled as [6]
effective thickness of the channel “pinchoff” region whose
√100 nm to
√300 nm. The factor
In (2), Vdsatis the potential at the channel “pinchoff” point.
Vdsat=
(Vgs− Vt)LEcr
Vgs− Vt+ LEcr
(3)
where Ecr is the critical field for velocity saturation and its
value is about 5 × 104V/cm.
In the earlier discussion, the only unknown parameter in (1)
is the coefficient C1(a process determined as constant). For
each technology, it only needs to be characterized once. The
typical values of C1are within 1.9–2 [7].
Besides the interfacetrap generation model given by (1), the
other two important models for hotcarrier effects are substrate
current (Isub) model and gate current (Igate) model
Isub=C2Idsexp
?
?
−
Φi
qλeEm
Φb
qλeEm
?
?
(4)
Igate=C3Idsexp
−
(5)
where Φiis the minimum energy (in electronvolts) for a hot
electron to create an impact ionization (Φi= 1.3 eV) and Φb
is the barrier energy (also in electronvolts) at the Si−SiO2
interface.
By defining the device hotcarrier lifetime tfas the time to
reach a fixed amount of interfacetrap density, we can combine
(1) and (4) into a very useful lifetime equation
tfIds
W
= C4
?Isub
Ids
?−Φit,e/Φi
.
(6)
Equation (6) is used in many hotcarrier reliability simulation
tools derived from BERT (Berkeley Reliability Tool) [9]. From
this equation, a very simple acceleratedlifetime model for HCI
can be obtained
tf= C5exp
?
θ
Vds
?
(7)
Page 3
100IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008
where C5and θ are technologyrelated constants whose values
are determined from acceleratedlifetime tests and Vdsis the
draintosource voltage. Equation (7) relates a device’s HCI
lifetime to only one operating parameter that can be directly
calibrated from SPICE simulation. The main problem for this
simple relation is that it is only valid for a small range of gate
voltages near the maximum substrate current [5].
To better capture hotcarrier stress profiles in real circuit
environment, a substrate current (Isub) model was proposed
in literature. Isub has been identified as the best hotcarrier
reliability monitor for nMOSFETs. According to [10], the
deviceparameter degradation due to HCI can be modeled as
?Isub
where Isub/W is the normalized substrate current and α, β, and
C6are technologyrelated constants.
Temperature acceleration is often treated as a minor effect
in most HCI models. However, if there are large temperature
excursions, we have to include temperature acceleration effects
in the HCI lifetime models [1]. The combination of temperature
effect and (8) produces a more comprehensive HCI lifetime
model
∆P = C6
W
?α
tβ
(8)
tf= AHCI
?Isub
W
?−n
exp
?EaHCI
κT
?
(9)
where EaHCI is the apparent activation energy (EaHCI can
be negative or positive depending on device technology, but
the typical values of EaHCIare within −0.1–−0.2 eV), W is
the device gate width, κ is Boltzmann’s constant (κ = 8.62 ×
10−5eV/K), T is the temperature in kelvin, n is a technology
dependent constant, and AHCIis the model prefactor.
There are two ways to determine Isub: one is from (4) and
the other is from BSIM3 model equations as follows:
Isub=α0+ α1Leff
Leff
V?
ds
?Ids0(1 + V?
× exp
?−β0
V?
ds
ds/VA)
1 + RdsIds0/Idseff
(10)
V?
ds=Vds− Vdseff.
(11)
The meaning of the earlier model parameters is given in
BSIM3 Model User Manual [11]. This BSIM3 Isubmodel is
quite similar to the Isubmodel proposed in iProbed [12].
The degradation of pMOSFETs under hotcarrier stress is
becoming one of the important contributors to circuit relia
bility. The hotcarrierinduced pMOSFET degradation effect
on circuit performance is different from that of nMOSFET in
that it may lead to reverse shifts (as compared to nMOSFET)
in device and circuit parameters due to significant negative
charge trapping in oxide. The circuitperformance degradation
can be characterized more accurately if pMOSFET HCI effect
is also considered. Even though the wearout dynamics and
deviceparameter degradation trends of pMOSFETs are differ
ent from those of nMOSFETs, with minor modifications, the
earlier nMOSFET’s acceleratedlifetime model can be applied
to pMOSFETs.
tf= AHCI,p
?Igate
W
?−m
exp
?EaHCI,p
κT
?
(12)
where EaHCI,p is the apparent activation energy (EaHCI,p is
within −0.1–−0.2 eV) and W is the device gate width. m and
AHCI,pare technologyrelated constants.
B. FailureEquivalent Circuit Model
To simulate the effect of device hotcarrier damage on cir
cuit functionality, the devicelevel wearout effects have to be
characterized with some additional circuit elements in device
SPICE model. Essentially, SPICEcircuit simulation is no more
than solving a group of devicemodel equations to predict the
interactions of all these devices upon external stimuli. There
fore, circuit functionality is determined by individual device
models. Circuit degradation or failures can be viewed as the
results that devicelevel wearout effects express themselves at
circuit level by changing their model structures. If the change of
device model structures due to wearout effects can be correctly
modeled with the inclusion of additional circuit elements and
the relations between these additional elements and the time
dependent wearout parameters can be built and calibrated with
simple testing work, then it is foreseeable that circuitreliability
simulation will become a natural and simple step of the overall
circuit functional simulation.
Failureequivalent circuit models emulate degradation of de
vice parameters with some additional lumped circuit elements
(resistors, transistors or dependent current sources, etc.). The
values of these additional lumped elements are determined
by devicewearout parameters (such as HCIinduced interface
traps ∆Nit), which are timedependent, and by device terminal
voltage and current waveforms. Therefore, at any time t, values
of these lumped elements can be accurately predicted, and their
magnitude reflects the devicewearout degree. The larger the
magnitude of these values, the severer the damage to circuit
functionality. As a result, circuit designers can quickly analyze
circuitreliability behaviors at any given time with these failure
equivalent circuit models.
Several HCI failureequivalent circuit models have been
developed in the past years and some of them have been built
into commercial reliability simulation tools. BERT is up to now
the most successful circuitreliability simulation tool. BERT
directly models nMOSFET hotcarrier damage in drain–current
degradation. The drain–current degradation ∆Idresults from
channelmobility degradation, which again results from HCI
induced interface traps ∆Nit. ∆Nitis modeled with the famous
Age parameter. In BERT, ∆Id is implemented as an asym
metrical voltagecontrolled current source in parallel with the
original nMOSFET. The pMOSFET HCI effect is modeled with
the concept of channel shortening and drainresistance increase
[9]. The BERT ∆Idmodel is shown in Fig. 1, which captures
the asymmetrical forward and reverse I–V characteristics and
allows simulation of devices undergoing bidirectional stresses
(such as devices in a transmission gate).
Page 4
LI et al.: COMPACT MODELING OF MOSFET WEAROUT MECHANISMS FOR CIRCUITRELIABILITY SIMULATION101
Fig. 1.
tionalinterfacetrapgenerationnearbothdrainandsource.LfandLrrepresent
forward and reverse hotcarrier damaged regions. (b) HCI drain–current ∆Id
failureequivalent circuit model [13], [14].
BERT nMOSFET HCI failureequivalent circuit model. (a) Bidirec
BERT ∆Idmodel is capable of characterizing bidirectional
hotcarrier stress effects. It requires extraction of six process
parameters from devicetesting experiments.
Experiments have proved that HCIinduced interface traps
in nMOSFET is localized above the channel near the drain
junction. More specifically, these interface traps are localized
in the vicinity within 100 nm from the drain [6]. Based on
this observation, Leblebici and Kang [7], [15] at University of
Illinois at UrbanaChampaign (UIUC) developed a two
transistor HCI failureequivalent circuit model which consists
of an HCIdamaged parasitic transistor with fixed channel
length L2(L2≈ 0.1 µm) in series connection with the original
transistor whose channel length is shrunk to L−L2. The pri
mary assumption for this model is that all generated interface
traps are occupied by electrons, which equals to considering
only negative fixed charge. The model is shown in Fig. 2.
From Fig. 2(a), the interfacetrapped charge Qitdue to HCI
can be readily derived as
Qit(x) = 0(13)
when (0 ≤ x < L1)
Qit(x) =QM
L2
(x − L1)
(14)
when (L1≤ x < L), where QM denotes the largest interface
charge, L1= L − L2, and L2represents the length of the dam
aged channel region. This twotransistor model characterizes
the amount of hotcarrier damage with only two parameters
Fig. 2.
oxidecharge distribution profile used in model derivation. (b) Crosssectional
view of nMOSFET with hotcarrier damage (L1 is the undamaged channel
region and L2is the damaged channel region). (c) Twotransistor series failure
equivalent circuit model. The parasitic transistor has different channel mobility
and threshold voltage with the channel length L2set to 0.1 µm [7], [12], [16].
UIUC nMOSFET HCI twotransistor series model. (a) Triangular
QM and L2. Therefore, the modelparameterextraction work
is greatly reduced. The drawbacks of this model are in two
aspects: the triangular chargedensity distribution is over sim
plified and it is not easy to extrapolate QMvalue.
Up to now, the simplest HCI failureequivalent circuit model
is the hotcarrierinduced seriesresistance enhancement model
(HISREM), which is also named as ∆Rdmodel [17]. Based on
the fact that the increase of HCIinduced series drain resistance
is due to the injection of hot carriers close to the drain edge,
a series resistance ∆Rd can be added to the drain of the
nMOSFET to emulate the process of hotcarrierinduced
interfacetrap generation, the channelmobility reduction, and
thresholdvoltage drifts. HISREM consists of a voltage
dependent drain resistor ∆Rd connected in series with the
original nMOSFET. ∆Rdis a function of the applied voltages
and the HCIinduced interfacetrapped charge ∆Nit. The be
havior of the damaged nMOSFET is emulated by the original
undamaged device operated with a reduced draintosource
voltage, which is controlled by this additional drain resistor
∆Rd. Because ∆Nit is a timedependent parameter, ∆Rd
model is able to predict drain–current degradation at any given
time. HISREM is capable of modeling selflimiting effects of
Page 5
102IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008
Fig. 3.
Vgs− Vt− Vdsand VRd= Ids∆Rd. Vtis threshold voltage, and Idsis the
current from node D to S.
HCI failureequivalent circuit model in SPICE. In the model: Vgdx=
hotcarrier damage, because the increase in series drain resis
tance of an nMOSFET suppresses hotcarrier stress. The main
feature of HISREM model is that there is only one parameter
∆Nitto be extrapolated from experiments.
For advanced technologies, we add an additional HCI
related factor, oxidetrapped charge ∆Nox, in ∆Rdto increase
accuracy in SPICE reliability simulation. Then, ∆Rdvalue is
determined by both interfacetrapped charge ∆Nitand oxide
trapped charge ∆Nox. The contribution of ∆Nox to device
wearout is often neglected, but recent experimental work recog
nizes that they can account for some of the observed enhanced
degradation effects in nMOSFETs which cannot be explained
solely by ∆Nitgeneration.
This new HCI failureequivalent circuit model is shown in
Fig. 3. The derivation of ∆Rdis carried out under the assump
tions that all interface traps are acceptorlike and occupied by
electrons,andchannelmobility degradation µiscaused byboth
∆Nitand∆Nox.Thefirstassumptionmeans thatthenetcharge
in interface traps is a fixed negative charge for nMOSFET in
strong inversion operation. The second assumption leads to the
following:
µ =
µ0
1 + α∆N
(15)
where ∆N = ∆Nit+ ∆Nox(in per square centimeter), µ0is
the original channel mobility, α is a processdependent con
stant, and α ≈ 2.4 × 10−12cm2[17].
The charge in conducting channel Qch(y) is modeled as
?
where Coxis the gateoxidecapacitance perunit area, Vch(y)
is the potential along the channel, and y is the horizontal axis
pointing to the drain and along the channel.
Applying gradual channel approximation (GCA) and com
bining (15), we can write the drain–current Idsin the following
format:
?
Qch(y) = −Cox
Vgs− Vt−q∆N
Cox
− Vch(y)
?
(16)
Ids=
µ0
1 + α∆NCoxW
L
Vgs− Vt−q∆N
Cox
−Vds
2
?
Vds.
(17)
In Fig. 3, nMOS is the undamaged device with mobility µ0
and threshold voltage Vt. The current from node D to S is
?
where VRdis the voltage drop across ∆Rd. Combining (17) and
(18) and, then, solving for VRd, we have
Ids= µ0CoxW
L
Vgs− Vt−Vds− VRd
2
?
(Vds− VRd)
(18)
VRd= −Vgdx
+
?
?
?
?V2
gdx+ 2Vds∆N
?
α?Vgdx+Vds
2
?
1 + α∆N
+
q
Cox
?
(19)
where Vgdx= Vgs− Vt− Vdsfor the linear region and Vgdx=
0 for the saturation region.
From (17), when ∆N = 0 at t = 0, we have the undamaged
drain–current Ids0flowing through the nMOS
?
If ∆N is small, from (17) and (20), we can get a simple
relation between fresh and degraded draintosource current
Ids0= µ0CoxW
L
Vgs− Vt−Vds
2
?
Vds.
(20)
Ids=
Ids0
1 + α∆N.
(21)
From the earlier equations, we can solve for ∆Rdas
∆Rd=1 + α∆N
Ids0
VRd
(22)
where Ids0is given by (20) and VRdis given by (19). In quasi
static operation, ∆N is a timedependent parameter. Thus,
∆Rdis also timedependent. At any time t, if ∆N is known,
∆Rdwill be solely determined.
The modeling of ∆Noxstarts from a simple injectioncurrent
model Iei, which describes 1D process of electron injection
into oxide based on quasielastic scattering assumption.
Iei=1
2
Ids
WL
tox
λrR2Pi(Eox)exp
?
−1
R
?
(23)
where L is the channel length, W is the channel width, Em
is given by (2), λr is the redirection meanfree path (λ =
61.6 nm), and toxis the oxide thickness. R = λEm/ϕb, where
λ is the scattering meanfree path of the hot electron (λ =
9.2 nm) and ϕbdenotes the silicon and oxide energy barrier
(ϕb≈ 3.2 eV for nMOSFET).
The most important term in (23) is Pi(Eox), which denotes
the probability that a hot electron can enter the gate oxide
by surmounting the surface potential barrier. An empirical
expression for Pi(Eox) is given by
Pi(Eox) =
αEox
1 + Eox/β×
1
1 +γ
Lexp(−Eoxtox/1.5)+ η
(24)
where Eox= (Vgs− Vds)/tox[7]. Equation (24) is for the case
of Eox≥ 0; if Eox< 0, then it is simplified to Pi(Eox) = η.