Mechanism of Electron Trapping and Characteristics of Traps in HfO2 Gate Stacks

IEEE Transactions on Device and Materials Reliability (Impact Factor: 1.54). 04/2007; DOI: 10.1109/TDMR.2007.897532
Source: IEEE Xplore

ABSTRACT Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.

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    ABSTRACT: We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO2/HfO2/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-the-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI.
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    ABSTRACT: Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.
    IEEE Transactions on Device and Materials Reliability 12/2013; 13(4):507-514. · 1.54 Impact Factor
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    ABSTRACT: service Email alerting click here in the box at the top right corner of the article or Receive free email alerts when new articles cite this article -sign up go to: ECS Journal of Solid State Science and Technology To subscribe to © 2012 The Electrochemical Society ECS Journal of Solid State Science and Technology, 1 (4) Q79-Q85 (2012) Q79 2162-8769/2012/1(4)/Q79/7/$28.00 © The Electrochemical Society Closed-form, textbook-appropriate equations have been derived for the drain current I D , the channel conductance g D , and the trans-conductance g m of high-k MOSFETs, incorporating high-k gate stack charges Q di,gsc , non-saturating inversion surface potential increase ϕ s,inv , and work-function difference φ MS . These ab initio relations, developed without imposing any assumptions, provide a clear view of the degrading effects of the high-k gate stack charges, the non-saturating inversion surface potential, and the semiconductor-metal work function difference on I D , g D , and g m . Rational estimates have been made of the latter which illustrate the relative weights of each of the three non-ideal factors in the degradation of the channel parameters of the high-k gate stack. The degradation appears to be most severe for the channel conductance, followed by the drain current, and then the trans-conductance. The work-function anomaly does not directly affect the trans-conductance for which the major degrading factor is the non-saturating surface potential. Even for moderate drain voltages, the numerical estimates reveal the drain current versus the drain voltage relation to become more non-linear in the case of the high-k gate stack. Comparison with the available experimental high-k gate stack data supports the import of these equations. © 2012 The Electrochemical Society. [DOI: 10.1149/2.010204jss] All rights reserved. Manuscript submitted April 30, 2012; revised manuscript received June The classical closed-form drain current versus the drain voltage relations for the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) were derived under the following assumptions: 1–3 1) No fixed or trap charges inside the bulk of the gate stack; 2) no inter-face traps or fixed charges at the semiconductor-dielectric interface; 3) saturation of the inversion surface potential to its value at the onset of strong inversion (ϕ s,inv,th) for the entire strong inversion regime; 4) no semiconductor-metal work function difference. None of the above assumptions is tenable in the case of MOSFETs with high-k gate stacks, which are beset with enormous bulk charges and traps and work-function anomaly. 4,5 After strong inversion sets in, the sur-face potential far from saturating has been observed to keep increas-ing continuously over the entire strong inversion regime. 6,7 Hence the above assumptions taken together represent a serious contradic-tion to the reality that obtains in the case of the current high-k gate stacks. Numerical models have been developed to make more realistic estimates of the drain current and the related parameters of MOS-FETs. However, closed-form, text-book type equations, derived from the first principles, are needed to provide a sound physical insight into the critical parameters. Needed are mathematical relations in closed form for the drain current I D , the channel conductance g D , and the transconductance g m which transparently illustrate how much the high-k gate stack charges, the non-saturating inversion surface poten-tial, and the work function anomaly degrade the channel parameters. Even the recent semiconductor device and gate stack reference books still present the classical closed-form equations for the MOSFET channel parameters. 8–10 The aim of this study was three-fold, namely to: (1) have direct incorporation of the threshold-excess inversion sur-face potential (ϕ s,inv = ϕ s,inv -ϕ s,inv,th), the total gate-stack charge density Q di,gsc , and the semiconductor-metal work-function difference φ MS in the equations for the drain current I D , the channel conductance g D , and the transconductance g m ; (2) illustrate the scale of degradation of I D , g D , and g m by the non-ideal factors of ϕ s,inv , Q di,gsc , and φ MS , by quantitative analysis and estimation, using the available experimental data; (3) present text-book-appropriate relations in such a form that, how much each of the adverse factors degrades each of the channel parameters, becomes visible in a glance.