Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.
", , , . It was reported that traps in HfO 2 are related to the oxygen vacancies located near or above the Si conduction-band edges, which allows efficient charge trapping to occur under the nMOS PBTI stress , . Therefore, the ionized oxygen vacancies work as the electron trap sites in HfO 2 and ZrO 2 . "
[Show abstract][Hide abstract] ABSTRACT: The effects of Zr composition on the crystallization behaviors and reliability characteristics of atomic-layer-deposited Hf<sub>1-x</sub> Zr<sub>x</sub>O<sub>y</sub> (0 ≤ x ≤ 1) gate-dielectric films are examined. n-Channel metal-oxide-semiconductor field-effect transistor (nMOSFET) devices with ZrO<sub>2</sub> gate dielectrics showed a much smaller V<sub>th</sub> shift under the positive bias stress compared with the same device with HfO<sub>2</sub> gate dielectrics. The impact of Zr composition on the crystallization temperature, crystalline phases, and surface morphology of Hf<sub>1-x</sub> Zr<sub>x</sub>O<sub>y</sub> films is studied. As the Zr composition in the Hf<sub>1-x</sub> Zr<sub>x</sub>O<sub>y</sub> films increased, the reduction of crystallization temperature and the transformation from a monoclinic to a tetragonal phase were observed. The grain size of the crystallized ZrO<sub>2</sub> film is much smaller than that of crystallized HfO<sub>2</sub>. The Hatband voltage (V<sub>fb</sub>) shift under positive gate-bias stress in p-channel MOS capacitor (pMOSCAP) devices show a similar trend to the Vth shift in nMOSFET devices. In addition, the annealed ZrO<sub>2</sub> films show a large reduction in the V<sub>fb</sub>, shift under the positive bias stress compared with as-deposited ZrO<sub>2</sub> in pMOSCAP devices. The improved bias-temperature-instability characteristics of ZrO<sub>2</sub> compared with that of HfO<sub>2</sub> is related to the smaller grain size of crystallized ZrO<sub>2</sub>.
IEEE Transactions on Electron Devices 08/2011; 58(7-58):2094 - 2103. DOI:10.1109/TED.2011.2136380 · 2.47 Impact Factor
"Indeed, although there is a broad consensus that charging of preexisting traps (Trapping-TP) and/or newly generated traps in the bulk oxide (Trap generation-TG) are responsible for the PBTI degradation [1-9], the identification of the (time) regimes dominated by the respective processes remains challenging; and this ambiguity leads to different types of PBTI models in the literature. Various version of TP-only theories      suggest a two step process: electrons are first trapped into preexisting bulk traps and they subsequently migrate to other pre-existing traps . Meanwhile, other groups observe steeper increase of PBTI degradation at very long time stress  or at shorter time, but at extreme stress conditions  . "
[Show abstract][Hide abstract] ABSTRACT: We report a simple but effective SILC-based methodology to separate and identify trapping and trap generation dominated regimes of positive bias temperature instability (PBTI). We use theoretical model and experiments to demonstrate that the sign for stress induced leakage current (SILC) reverses as PBTI transitions from trapping to trap generation dominated regimes; this is in contrast to threshold voltage shift with no corresponding sign reversal. SILC crossover methodology further verifies that initial and fast saturated trapping is temperature independent while trap generation is voltage and temperature activated. The SILC-based reassignment not only indentifies trapping and trap generation regimes of PBTI, but also suggests a remarkable universality of trap generation in wide variety of High-k samples.
"Applying PBTI stress to high-k/metal-gate NMOSFETs causes electrons in the inversion layer to gain sufficient energy to be injected into the dielectric layers. As a result, electrons are easily trapped in the oxygen vacancies within the high-k film  . "
[Show abstract][Hide abstract] ABSTRACT: This study examines the effects of plasma-induced damage (PID) on Hf-based high- k /dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high- k /metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high- k /metal-gate CMOS technology.
International Journal of Plasma Science and Engineering 01/2009; 2009. DOI:10.1155/2009/308949
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.