Article

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

Texas Instrum. Inc., Dallas, TX, USA
IEEE Transactions on Device and Materials Reliability (impact factor: 1.54). 10/2004; DOI:10.1109/TDMR.2004.837210
Source: IEEE Xplore

ABSTRACT We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows ∼1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 1013 write/read polarization switching cycles. Retention measured after 1012 switching cycles demonstrates no degradation relative to arrays with minimal cycling.

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Keywords

130-nm CMOS logic process
 
70-nm thick MOCVD PZT ferroelectric films
 
arrays
 
Excellent bit endurance properties
 
imprint effect
 
memory arrays
 
minimal cycling
 
packaged memory arrays
 
shows ∼1.5 eV time-to-fail activation energy
 
temperature bakes