A New Linearization Technique for CMOS RF Mixer Using Third-Order Transconductance Cancellation
ABSTRACT A new third-order transconductance (gm3) cancellation technique is proposed and applied to a conventional radio frequency (RF) mixer for improving circuit linearity. The bulk-to- source voltage is applied to adjust the peak value position of gms. The cancellation of gm3 is utilized by a negative peak gm3 transistor combined in parallel with a positive peak gm3 transistor. For a single device, the measured adjacent channel power ratio (ACPR) and third-order intermodulation (IMD3) distortion are both improved over 15 dB. A Gilbert-cell mixer in commercial 0.18-mum CMOS process was designed using the proposed method to further evaluate the linearity. The compensated gm3 device is placed in the input RF gm-stage and then reducing the principle nonlinearity source of the mixer. From the experiment results, the ACPR and IMD3 of the mixer are improved about 10 and 15 dB, respectively.
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ABSTRACT: CMOS cascode device pairs are widely used in many applications. To improve the linearity of the cascode amplification cell while maintaining reasonable gain, a new technique, called splitting cascode, is proposed in this paper. The original cascode is split into two sub-cells to investigate the linearity behavior. With this technique, the third-order intermodulation (IM3) distortion of a cascode amplifier can be greatly improved by 29 dB at 56 GHz. Due to its simple structure, yet significant linearity improvement to the traditional cascode cell, this novel technique can be used in almost every circuit where the cascode cell is used to amplify a signal. To measure the effect of reduction of the IM3 distortion after linearization, two sub-harmonically pumped down conversion mixers are applied to convert the signal to lower frequency. If the mixers are driven by two local oscillator signals with 45 <sup>°</sup> phase difference, the whole circuit forms a 60-GHz demodulator. The measurement results show an improvement in the IM3 distortion level of more than 20 dB from 54 to 66 GHz. The measurement results show the proposed method can bring linearity improvement in wide input power range. To the authors' knowledge, this is the first linearization method realized in CMOS technology with an operation frequency around 60 GHz.IEEE Transactions on Microwave Theory and Techniques 03/2011; · 2.23 Impact Factor
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ABSTRACT: Thisletterpresentsa -cancellationrangeextension methodwithbulk-biascontrolthatwasappliedtoaMultipleGated Transistors (MGTR) technique, which is a linearity enhancement technique for RF amplifiers. Instead of adjusting the gate-biasing voltage of the auxiliary transistor (AT) in conventional -cancellation, we propose to use the bulk-biasing voltage, , which allows for range extension of the -cancellation of AT. The proposed technique does not require any other additional biasing circuits and has the benefit of consuming less power. The proposed low noise amplifier (LNA) is implemented in 0.18 1-poly-6- metal CMOS technology. Our results show that the LNA achieves a noise figure of 1.76 dB, a 12.45dBm input third order intercept point (IIP3), and a15 dBpower gain at 0.9GHz, with the core LNA consuming 4.5 mA from a 1.5 V power supply.IEEE Microwave and Wireless Components Letters - IEEE MICROW WIREL COMPON LETT. 01/2011; 21(11):616-618.
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ABSTRACT: This paper presents linearity enhancement of CMOS device for microwave amplifier applications. The proposed method is based on a modified third-order transconductance (g<sub>m3</sub>) cancellation technique and the device is fabricated in a 0.13 μm CMOS process. For the NMOS device with the proposed g<sub>m3</sub> cancellation technique, the third-order intermodulation distortion (IMD3) is improved by 15 dB as compared to the conventional single device. Two Ka-band CMOS amplifiers with and without the linearization are successfully evaluated. With the linearization, the measured IMD3 is enhanced by 14 dB, and the adjacent channel power ratio (ACPR) of the amplifier is improved by 7 dB for a 64-QAM modulation signal. Moreover, the linearization scheme is easily applied to the microwave amplifier and mixer designs without extra dc power consumption.Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International; 07/2011
350IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 5, MAY 2008
A New Linearization Technique for CMOS RF Mixer
Using Third-Order Transconductance Cancellation
Kung-Hao Liang, Student Member, IEEE, Chi-Hsein Lin, Student Member, IEEE, Hong-Yeh Chang, Member, IEEE,
and Yi-Jen Chan, Senior Member, IEEE
Abstract—A new third-order transconductance ?
lation technique is proposed and applied to a conventional radio
frequency (RF) mixer for improving circuit linearity. The bulk-to-
source voltage is applied to adjust the peak value position of
The cancellation of
and third-order intermodulation (IMD3) distortion are both im-
proved over 15 dB. A Gilbert-cell mixer in commercial 0.18- m
CMOS process was designed using the proposed method to fur-
ther evaluate the linearity. The compensated
in the input RF gm-stage and then reducing the principle nonlin-
earity source of the mixer. From the experiment results, the ACPR
and IMD3 of the mixer are improved about 10 and 15 dB, respec-
?is utilized by a negative peak
?device is placed
Index Terms—CMOS, harmonic, third-order intermodula-
tion (IMD3), intermodulation, linearization, mixer, third-order
of signal-to-noise ratio (SNR), especially for high-level
modulation schemes, such as orthogonal frequency division
multiplexing signals. In general, the linearity of the transceiver
is dominated by mixers and power amplifiers . Therefore, a
mixer with good linearity is desired to further enhance the SNR
of the RF output signal. Gilbert-cell mixers are widely used
as the down-converter in CMOS transceivers, since they are
broadband with good conversion gain . So far, few lineariza-
tion techniques have been proposed using CMOS processes for
the RF mixer applications –. The linearity was improved
to various degrees by using these techniques, but they made the
circuits more complex with additional dc power consumption
In this letter, an innovative linearization method using a
is applied to bulk-to-source voltage
of the device, and also the characteristic of
IGH linearity transceivers are essential for high data
rate communication systems due to the requirement
to adjust threshold
Manuscript received October 1, 2007; revised January 29, 2008. This work
wassupported in partbythe National ScienceCouncil ofTaiwan,R.O.C., under
Grants NSC 96-2221-E-008-117-MY3, NSC 96–2221–E-008–119–MY3, and
NSC 96-2628-E-008-073-MY3 and by the Taiwan Semiconductor Manufac-
turing Company through the Chip Implementation Center (CIC) of Taiwan.
tral University, Jhongli 32001, Taiwan, R.O.C. (e-mail: firstname.lastname@example.org.
Color versions of one or more of the figures in this letter are available online
Digital Object Identifier 10.1109/LMWC.2008.922129
can be further adjusted to enhance the linearity of the device.
The transistors with negative and positive
get a flat
region, and the overall
nection of transistors will be close to zero. In the operation re-
gion, the nonlinear characteristics of
the intermodulation distortion of the device will also be further
reduced without additional dc power consumption due to the
proposed topology. To evaluate the linearization technique, a
Gilbert-cell mixer based on the proposed method has been suc-
cessfully demonstrated. Also, the proposed mixer is very suit-
able for the applications of the high linearity transceivers due to
its superior linearity, conversion gain and bandwidth.
are combined to
of the parallel con-
can be cancelled, and
II. LINEARIZATION METHOD AND MIXER DESIGN
The drain current of a common-source MOSFET can be ex-
pressed by using a Taylor series expansion as follows:
is gate-to-source voltage, and
-order transconductance. The third-order coefficient
performs an important role in the third-order intermodulation
distortion of an amplifier . Assuming the drain is shorted
at the signal frequency, the third-order intercept point (IP3) of
gate voltage amplitude can be given as follows 
As can be observed, the IP3 of the device can be improved
effectively. A TSMC 0.18- m 1P6M CMOS
technology is used to evaluate the characteristic. Fig. 1 shows
gate width of the NMOS device is 2.5 m with 35 fingers. The
has a positive peak value at the gate voltage of 0.45 V, and
it will be close to zero near the threshold voltage. The amplifier
is usually operated in therange of 0.6 and 0.8 Vfor high voltage
or power gain, but the
usually has a negative peak value in
this bias region, and also the linearity of the circuit is degraded.
is the third-order derivative of the drain current
versus gate bias, the characteristic of
varying the threshold voltage. The measured
bulk-to-source voltage is
1 V applied to 37.5- m gate-width
device; the bulk-to-source voltage of the 50- m gate-width de-
vice is 0 V. The solid circle-symbol curve shows the compensa-
tion result of
with a total gate-width of 87.5 m. Because
the positive and negative values of
different sizes of the two transistors are selected to obtain a flat
characteristics versus gate-to-
can be adjusted by
are not symmetrical, the
1531-1309/$25.00 © 2008 IEEE
LIANG et al.: NEW LINEARIZATION TECHNIQUE FOR CMOS RF MIXER351
Fig. 1. Measured ? , ?
20 fingers in parallel with a unit gate width of 2.5 ?m.
characteristics of two transistors of 15 and
Fig. 2. Measured ?
compensation results of two connected in parallel tran-
nonlinear characteristics of
The proposed method is applied to a Gilbert-cell mixer as
shown in Fig. 3. The mixer consists of four major parts:
transconductance stage (
, output load (
and). The transconductance stage performs as a
voltage-to-current converter, and the device is essentially bi-
ased in the active region to achieve high conversion gain with
low noise figure. Most of the distortion in a mixer comes from
the transconductance stage , and therefore the linearity of
the mixer can be enhanced using a good linearity device for
the transconductance stage. The proposed
applied to thiscircuit, and thegate widthsof the parallel transis-
tors are 2.5 m with 15 and 20 fingers, respectively. As shown
in Fig. 2, the transconductance stage can have a flat
by supplying a bulk-to-source voltage to one of the transistors.
The linearization method does not require additional power
consumption, because the total gate width of the paralleled pair
is equal to the original device size of transconductance stage
(i.e., 35 fingers). The transistors
pinch-off region to act as switches and are controlled by the
LO signals. The output resistors
intermediate frequency (IF) from current signals to voltage
signals. The common-source transistors
as output buffers to achieve the impedance match for driving
approximately equal to zero. By canceling the
, the linearity of device can be
), switching stage
) and output buffers
are biased at near
andare used to transfer
Fig. 3. Schematics of the proposed highly linear RF mixer.
Fig. 4. IIP3 comparison of the transistors with and without ?
are biased at 1.8 and 0.65 V, respectively.
load . An on-chip bypass capacitor is included
and ground for the in-band bypass.
III. EXPERIMENTAL RESULTS OF DEVICE AND MIXER
Fig. 4 shows the measured fundamental output power and
IMD3 of the transconductance stage (
of the stage are 1.8 and 0.65 V, respectively. The mea-
sured IMD3 is improved about 18 dB from
and the input IP3 is also improved by 8 dB. The improvement
of the IP3 is also evaluated using a third-order intermodulation
formula, and the calculation is also close to the IP3 extracted
result. A digital modulation (NADC) signal measured is also
used to evaluate the linearity, and the measured result is shown
in Fig. 5. Assuming channel bandwidth and spacing are both
48.6 kHz, the measured ACPR is enhanced by 15 dB with the
proposal cancellation technique. The output signal is also de-
modulatedusinga HP89441Avectorsignal analyzer ata center
frequency of 2.4 GHz.
Fig. 6 shows the chip photograph of the proposed mixer with
a chip size of 0.72
0.93 mm , where the core area of the
mixer is 0.2
0.26 mm . The chip was measured via on-wafer
probing in the RF and LO input ports. The differential IF output
signals are connected with an off-chip broadband balun via
and ), and the
and the gate-to-source voltage
48 to 66 dBc,
352 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 5, MAY 2008
Fig. 5. Measured ACPR results of the transistors with and without ?
Fig. 6. Chip micrograph of the highly linear mixer with a chip size of 0.72 ?
0.93 mm , and a core area of 0.2 ? 0.26 mm .
Fig. 7 Comparison of measured IIP3 between with and without ?
tion for the mixer.
bonding wires. For a fixed IF frequency of 100 MHz, the mea-
sured maximum conversion gain and noise figure are 11.2 dB
and 13.8 dB, respectively. The port-to-port isolations (RF-IF,
LO-IF and LO-RF) are better than 35 dB at 2.4 GHz. The dc
is 2 V with a 7.4-mA drain current, and
the gate-to-source voltage
The measured input IP3 and ACPR of mixer are plotted in
Fig. 7 and Fig. 8, respectively. The measured IIP3 and ACPR
of the stage is also 0.65 V.
Fig. 8. Measured ACPR results of the mixer at an IF frequency of 100 MHz.
are both improved by 10 dB. With and without the proposed
cancellation, the measured conversion gain and noise
figure are degraded by only 1.8 and 1.3 dB, respectively, and
the dc power consumption is almost same for both conditions.
it was also successfully demonstrated in a Gilbert-cell mixer.
The proposed method is easily applied to RF and microwave
circuit designs, and the linearity of the circuits can be highly
improved without consuming extra dc power consumption and
cost. In the future works, this technique will be utilized for the
to further enhance the linearity.
cancellation method is proposed in this letter, and
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