Uniformity of an Electroless Plated Ni on a Pad Connected to Different Size Pads or a Pn Junction for Under Bump Metallurgy in a Flip-Chip Assembly
ABSTRACT We investigated electroless Ni uniformity on Al metal pads connected to different size pads or a pn junction for under bump metallurgy in flip-chip assemblies. In an electrically isolated pad, Ni thickness decreased as the pad size decreased. Because of nonlinear diffusion of Pb2+ stabilizer in the plating solution, fewer electrons were supplied to the smaller pad than to the larger pad by an anodic oxidation reaction on the pad surface. In pads smaller than 50 mum square, the Ni thickness increased when connected to a 100 mum square pad. This increase might be caused by electrons flowing from the 100 mum square pad to the smaller pad to produce an equipotential for the connected pads. In addition, the Ni thickness was increased by electrical connection to an n-type Si in the presence of fluorescent light illumination for a pn junction area larger than 100 mum2. For a pad connected to a p-type Si, however, Ni thickness decreased in comparison to that of an electrically-isolated pad, regardless of the light illumination or pn junction area. The change of Ni height on pads connected to the pn junction is attributable to photoelectrons injected into the n-type Si, or to electron-hole recombination in the p-type Si. These results indicate that the pads should be of the same size within a chip for better Ni uniformity. Moreover, blocking light during Ni electroless plating can eliminate Ni thickness differences due to an n-type Si connection.
Conference Paper: Low-cost TSV process using electroless Ni plating for 3D stacked DRAM[Show abstract] [Hide abstract]
ABSTRACT: Three-dimensional integration using through-silicon vias (TSVs) has been widely developed. However, the additional cost of fabricating TSVs is one of the main factors that prevent the use of TSVs in large-scale integrated circuits (LSIs). In this paper, we propose a new and inexpensive TSV process in which TSVs and back-bumps are simultaneously fabricated using electroless nickel electroless palladium immersion gold plating. During this process, Ni is plated onto W pads on the back of Si. We successfully fabricated uniform TSVs and back-bumps by optimizing the fabrication process, which included implementing light-shield plating and performing annealing after plating. We fabricated two types of eight-stacked dynamic random access memories (DRAMs), one using poly-Si TSVs and one using Ni TSVs, and compared the operation of each type of DRAM.Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th; 07/2010
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ABSTRACT: We evaluated high frequency signal transmission characteristics of coplanar waveguides fabricated using Au cone bump interconnections. Electroless Ni / Au bumps were used as counter-electrodes against the Au cone bumps. The signal transmission loss increased with the number of bump interconnections. At 40 GHz, the signal insertion loss due to the bump interconnections was 0.017 dB / bump with the 10 μm square size Ni / Au bumps. This value was small enough for application to radio-frequency devices. While, with the 5 μm square size Ni / Au bumps, open failure was observed between the bump interconnections. The open failure might be caused by decreasing of the contact pressure between the bumps, due to the mushroom-like shape of the Ni / Au bumps.3D Systems Integration Conference (3DIC), 2011 IEEE International; 01/2012
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ABSTRACT: We describe a process for selective metallization of paper substrates bearing inkjet printed patterns of a commercial Pd/Sn colloidal catalyst ink plated using a commercial electroless Cu bath. The electrical conductivity of the Cu films is analyzed as a function of feature geometry (line dimensions (L) and spacing (S)), type of paper (P), age of the Pd/Sn patterns (A), plating time (T), and plating temperature (H) using a two-level factorial design. Conductivity is influenced predominantly by the P, T, and H factors, with lesser contributions attributed to pair-wise interactions among several of the variables studied. Increases in T and/or H enhance conductivity of the Cu films, whereas increases in P, corresponding to the use of rougher, more porous, paper substrates, yield Cu films exhibiting decreased conductivity. Our analysis leads to a model that predicts Cu film conductivity well over the ranges of variables examined, provides guidelines for identification of optimum conditions for plating highly conductive Cu films, and identifies areas for further process improvement.ACS Applied Materials & Interfaces 05/2012; 4(5):2358-68. DOI:10.1021/am3006934 · 6.72 Impact Factor