90IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003
Over GHz Electrical Circuit Model of a High-Density
Multiple Line Grid Array (MLGA) Interposer
Seungyoung Ahn, Junho Lee, Junwoo Lee, Jonghoon Kim, Student Member, IEEE, Woonghwan Ryu,
Byung-Hun Kum, Hyun-Seok Choi, Chong K. Yoon, and Joungho Kim
Abstract—The multiple line grid array (MLGA) interposer
was recently introduced as a future high-density high-speed
bonding method. In this paper, we introduce an electrical model
and high-frequency characteristics of the MLGA interposer.
High-frequency electrical model was extracted from microwave
-parameter measurements up to 20 GHz as well as from fun-
damental microwave network analysis. For the parameter fitting
process during model extraction, an optimization method was
used. Several different types of MLGA interposers were designed,
assembled and tested. The test vehicles contained coplanar
waveguides, probing pads and an MLGA interposer structure.
The height of the MLGA, the conductor shape inside the MLGA,
and the dielectric insulator of the MLGA were varied. From
the model, an MLGA with a height of 0.4 mm and a polymer
dielectric insulator was found to have 203 pH of self inductance,
49 pH of mutual inductance with the nearest ground conductor
line, and 186 fF of mutual capacitance. By reducing the height
of the MLGA and by using an insulator with a lower dielectric
constant, parasitic inductance and capacitance is further reduced.
TDR/TDT simulation and measurement showed the validity
of the extracted model parameters of the MLGA interposer.
Circuit simulation based on the extracted model revealed that the
MLGA interposer could be successfully used for microwave device
packages up to 20 GHz and for high-speed digital device packages
with a clock cycle up to 5 GHz.
Index Terms—Equivalent circuit model, GHz frequency, high-
density package, multiple line grid array (MLGA),
Semiconductor Industry Association (SIA) predicts that in
the near future packages of more than two thousand I/Os and
with more than one gigahertz off-chip clock frequency will be
introduced. To date, ball-type grid array (BGA) packages have
been used predominantly to meet current high-density package
requirements. A BGA has a smaller feature size and narrower
spacing than conventional bonding methods and, consequently,
it has desirable electrical transmission characteristics and very
small parasitic effects . However, single-chip packages using
a BGA with 0.65 mm pitch are still at the research stage and a
BGA with 0.50 mm pitch is not expected to be in commercial
N RECENT years, the demand for high-density packages
with many hundreds of I/Os has steadily increased. The
Manuscript received December 1, 2002; revised March 4, 2003.
S. Ahn, J. Lee, J. Lee, J. Kim, W. Ryu, and J. Kim are with the Terahertz
Interconnection and Package Laboratory, Department of Electrical Engineering
and Computer Science, Korean Advanced Institute of Science and Technology,
Taejon 305-701, Korea (e-mail: firstname.lastname@example.org).
B.-H. Kum, H.-S. Choi, and C. K. Yoon are with Glotech, Inc., Seoul, Korea
Digital Object Identifier 10.1109/TADVP.2003.811554
production until 2010. The density provided by the BGA
package is still not sufficient to satisfy the foreseen needs of
high-density and high-speed packages.
Recently, a new type of high-density interposer, called a
multiple line grid array (MLGA) interposer was introduced.
This is a candidate to replace the BGA package by further
reducing the bonding pitch. In addition, the height of the
bonding structure can be controlled independently, reducing
the parasitic inductance and capacitance at high frequency and
enhancing the transmission properties at microwave frequen-
cies . The MLGA interposer has a nonball-type bonding
structure, where thin conductor lines of cylindrical shape are
used for bonding instead of the spherical shape of conventional
ball-type bonding. An MLGA has many multiple line grids
(MLGs), as shown in Fig. 1, and each MLG has eight conductor
lines with a column type. The cylindrical conductor lines have
either a circular or semi-circular cross section, as shown in
Fig. 1(a). The space between the conductor lines is filled with
either a ceramic or polymer dielectric insulator. A ceramic or
polymer insulator can be chosen depending on cost, capacitive
loading and the possibility of embedding passive devices inside
the MLG. The eight conductor lines of the MLG are made of
Sn/Pb/Ag metal alloy.
An MLGA interposer is basically designed as a second-level
bonding method that connects the bonding pads of a package
substrate to the bonding pads of a PCB substrate. Bare dies
are mounted on the package substrate either using either wire
bonding or flip-chip bonding. An MLGA interposer was assem-
bled containing twenty-five MLGs. Each MLG had eight con-
ductor lines, giving two hundred I/Os in an MLGA package. By
increasing the number of MLGs in an MLGA package, many
thousands of I/Os can be easily manufactured. As shown in
Fig. 1, the pitch between the conductor lines in the MLG was
0.8 mm. An MLGA with a 0.4 mm metal line pitch has already
been successfully manufactured; this means it is possible to fur-
ther decrease the pitch of the metal conductor lines and to en-
hance the I/O density. Moreover, the controlled height of the
MLGA bonding varied from 0.2 mm to 0.5 mm. The height of
the MLGA bonding was smaller than the size of the solder ball
of conventional BGA bonding, resulting in lower parasitic ef-
fects compared to that of conventional ball-type bonding.
The most unique and important feature of the MLGA
package is the possibility of embedding passive devices inside
the MLGA, which is not possible in a conventional bonding
structures such as wire bonding, BGA or flip-chip bonding.
The MLG is manufactured using either a multi-layer ceramic
process or a multi-layer polymer process. When the MLGA
interposer is fabricated using a multi-layer ceramic process,
multi-layer parallel plate capacitors, termination resistors,
1521-3323/03$17.00 © 2003 IEEE
AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL91
block of the MLGA interposer. (b) Three types of MLG used in high-frequency
electrical modeling. Conductor shapes and the dielectric insulators are varied.
(c) Cross-sectional structure and dimensions of the assembled MLG used in
high-frequency electrical modeling.
(a) Structure and dimensions of the MLG used as the basic building
spiral inductors and filters can be embedded in the MLGA
interposer. The values of the embedded passives are estimated
in . In this research, we have shown that 138.6 pF of capaci-
tance or236.6 nHof inductancecan be embedded inan MLGof
1 mm height. For the packaging of high-speed digital devices,
integrated passive devices are attracting more interest because
devices that are more passive are required and these determine
the performance of high-performance systems. The passive
devices are used for signal line terminations, power/ground
noise decoupling and filtering. The passive devices are required
to have minimal unwanted parasitic effects, especially parasitic
inductance. A fundamental method for minimizing parasitic
inductance is to place the passive devices close to the die.
Conventional bonding methods serve only as an electrical
connection for the signal lines and power/ground lines. The
MLGA interposer provides not only electrical interconnections
with low parasitic effects but also an integrated passive device
carrier. According to reference , the decoupling capacitor in
the MLG is expected to improve the noise performance of the
package significantly. More than 47% of the power line voltage
fluctuation is reduced using an embedded decoupling capacitor
in an MLG. In addition, vertical transmission line structures
can be realized inside an MLG, enhancing the electrical trans-
mission characteristics at high frequency. Transmission line
structures can be implemented inside an MLG, by grounding
conductor lines around an active conductor line in an MLG.
To apply these high-density bonding techniques to high-per-
formance systems, including the BGA and the MLGA, accurate
and reliable electrical models of such bonding structures are
required. With precise models, the performance of the system
containing the packages can be accurately predicted and evalu-
ated. Electrical models of the BGA package have been reported
, . In this paper, we investigate the high frequency char-
acteristics of an MLGA interposer and derive equivalent circuit
models. First, the basic configuration of the equivalent circuit
was developed on the basis of the physical structure of the inter-
poser. The parameters in the configuration-based circuit model
were then fitted to the experimentally derived parameters using
The experimental parameters were measured using -param-
eter measurements and microwave network analysis. A similar
modeling procedure has been already proven successful in the
modeling of flip-chip bond modeling , , . Test samples
containing the MLGA interposer, package substrate, and PCB
have followed an accurate optimization process.
As a result of the -parameter measurement and model pa-
rameter extraction procedure, the self inductance of a conductor
line inside the MLG was found to be 203 pH for a 0.4 mm high
MLGA to0.2mm,theself inductancewas decreasedto 120pH.
The mutual inductance between the signal line and the nearest
ground line was 49 pH for a 0.4 mm high MLG and 29 pH for
0.2 mm high MLG. The mutual capacitance between the con-
ductor lines in the MLG was 186 fF in a 0.4 mm high MLGA
with a circular conductor and a polymer insulator, and 175 fF
for an MLGA with a height of 0.2 mm.
II. FABRICATION AND ASSEMBLY PROCESS
Fig. 1 is a schematic diagram showing the configuration and
the dimensions of the MLGA interposer and its bonding struc-
ture. Each MLG consisted of a dielectric insulator and eight
metal conductor lines inside the dielectric insulator. A number
of MLGs construct a complete MLGA. Although eight metal
conductor lines were used in each MLG in this study, as shown
in Fig. 1, more than a hundred I/O lines can be merged into an
MLG by enlarging the size of the MLG and by distributing the
conductor holes. Two different types of MLG were fabricated
for the modeling study. One consisted of a 2 mm
the other was a 2.45 mm
2.45 mm MLG with eight conductor
lines in a circular cross section, as shown in Fig. 1(b). In both
cases, the pitch and diameter of the conductor lines were the
board made of polymer BT resin. The height of the MLG was
chosen between 0.2 mm and 0.5 mm. The height of the solder
that bonded the package substrate pads to the MLG conductor
lines, as well as the MLG conductor lines to the PCB pads, was
2 mm MLG
92IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003
Fig. 2. Assembly process of the MLGA interposer.
0.2 mm, as shown in Fig. 1(c). Hence, the total height of the
MLGA interposer was controllable from 0.9 mm ( ; height of
mm) to 0.6 mm (
From previously reported heat sink simulations , the heat
generated by the chips mounted on the package substrate is
transferred to the PCB substrate through the package substrate,
the solder pad and the metal conductor lines in the MLG. As the
cross section of the circular conductor lines is larger than that
of the semi-circular conductor lines, the 2.45 mm
dielectric insulator with a circular cross-sectional metal line has
a better performance in terms of heat conductance. In addition,
since the reliability of the solder bump sandwiched between the
MLG and the package substrate depended on contact size, the
MLG that used the circular conductor had a larger contact area
and, hence, had a potentially higher yield.
Two types of material were used for the dielectric insulator
of the MLG. One type of MLG was made using a BT resin
polymer insulator, and the other type of MLG was made using
an alumina ceramic insulator. The dielectric constants of the
BT resin and the alumina were 4.5 and 9.6, respectively. The
holes for the conductor lines in the alumina insulator were
drilled using a laser beam of 250 m diameter, while the holes
in the polymer insulator were punched mechanically with
m diameter punch. Metal Ag/Pt was painted on the
walls of the holes, and the holes were then filled with a solder
alloy of Sn/Pb/Ag. When BT resin was used for the MLGA
package, the parasitic capacitance of the bonding structure was
reduced in comparison to that of the alumina insulator. This
lower parasitic capacitance decreases the output load of the IC,
decreases the propagation delay and increases the impedance of
the lines. The MLGA interposer that used the BT resin polymer
insulator showed a higher reliability in temperature cycling
fatigue tests with a dwell time of 15 minutes and a temperature
25 C and 125 C . Conversely, the thermal
conductivity of the ceramic insulator was higher, although the
embedded passives were more easily accommodated using the
MLGA package is presented in Fig. 2. Interconnecting methods
on which the IC was mounted and bonded, and (b) the lower side of the
MLGA interposer substrate after the assembly process of Fig. 2 was finished.
The substrate routing was designed using double-sided layers. The assembled
MLGA interposer has 25 (five rows ? 5 columns) MLGs and each MLG
contains eight conductor lines, resulting in a total of 200 I/O connections.
Photographs of (a) the upper side of the MLGA interposer substrate
Fig. 4. Overall schematic of the assembled MLGA interposer.
such as wire bonding or flip-chip can be used at the first-level
re-flow process was then employed at about 220 C to 230 C
to connect the MLGs to the pad of the PCB substrate. The same
process was then repeated on the package substrate; this step
was followed by the same re-flow process, which completed the
strate on which bare dies were mounted and bonded. Fig. 3(b)
is a photograph of the bottom side of the package substrate on
were bonded to the package substrate, and each MLG had eight
semi-circular conductor lines, as shown in the figure. A total of
200 I/O connections were placed in this MLGA package. The
size of the package substrate was 16.5 mm
pitch of the MLGs was 2.75 mm.
the MLGA interposer was used as a second-level package.
The signal from the IC chip went through the wire-bonding or
16.5 mm. The
AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL93
in the electrical modeling of the MLG interposer.
Extraction procedure for the equivalent circuit model parameters used
flip-chip bonding, as well as through the microstrip line and
the via on the package substrate, the conductor line inside the
MLG and the microstrip lines on the PCB substrate. To reduce
the parasitic effects of the MLG bonding and the size of the
package, the height of the MLG was reduced from 0.5 mm to
0.2 mm, which resulted in a reduction of height for the total
MLGA package, including the solder bump, from 0.9 mm to
III. TEST DEVICE AND MODEL PARAMETER EXTRACTION
The sequence of the model parameter extraction procedure
is illustrated in Fig. 5. From step 1 to step 3, we used a vector
network analyzer to measure the complex -parameters of the
test vehicle, which included a series connection of the coplanar
waveguide on the package substrate, an MLG interposer and a
coplanar waveguide on the PCB substrate.
From the physical configuration of the MLG structure, an
In the proposed circuit configuration, the circuit parameters are
mutual inductance and mutual capacitance. Since the length of
the MLG was much less than the wavelength that corresponds
to the spectral range, the suggested model is considered accept-
able. At this stage, the values of the lumped model parameters
are not determined.
Next, we calculated the -parameters of the same structure
based on equivalent circuit model parameters with consid-
eration of the physical structure and dimensions of MLGA
bonding. We measured the -parameters of the coplanar wave-
optimization process. From the proposed model configuration,
the -parameters were calculated using a microwave simulator
in step 6. Finally, the model parameters in the proposed circuit
model were fitted to the measured parameters by matching
the measurement-based -parameters and configuration-based
-parameters using an optimization option of the microwave
simulator in step 7. The procedures for extracting the model
parameters were applied to the five different MLGA devices
used in the test; the conductor lines and dielectric insulators
of these devices had different heights and shapes. After the
extraction of the equivalent circuit model parameters using the
optimization process, we conducted time-domain reflection and
transmission measurement. We then compared the waveforms
with the reflection and transmission waveforms that were
simulated using equivalent circuit model parameters extracted
in step 8.
The structure of the test device is shown in Fig. 6, which il-
lustrates the package substrate design, the PCB substrate de-
sign and the microwave probe positioning. A high-bandwidth
ture because the CPW is compatible with a G-S-G probe of
the -parameter measurement instrument and does not require a
multi-layer design. The CPW had a length of 4 mm, a width of
m and spacing of 50 m. Twenty-five MLGs were used
for the ground connection. In an MLG, only one out of eight
conductor lines was used as a signal connection, and the other
seven were used as a ground connection. As shown in Fig. 6,
we used 25 MLGs as a ground connection for low impedance
between the package substrate and the PCB substrate. Because
of the multiple through-hole vias on the package substrate and
multiple connections to the PCB substrate, negligible ground
impedance between the two probes was achieved. The -param-
eters were measured up to 20 GHz using 150
tips. Both substrates were made using a double-sided BT resin
) that was 0.4 mm thick.
By considering the physical structure and dimensions of the
MLGA interposer, we proposed a schematic of the equivalent
circuit model, as shown in Fig. 7. The numbering of the eight
conductor lines inside the MLG is shown in Fig. 7(a), and the
proposed model circuit is shown in Fig. 7(b). The self induc-
tance of a conductor line is characterized by inductor
self inductance of a via on the package substrate is character-
ized by inductor
. The parameter
tual inductance between the inductances of the conductor lines,
m pitch probe
, and the
represents the mu-
94 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003
in the circuit model analysis and their number assignment. (b) Suggested
configuration-based equivalent circuit model of the MLG. The suggestedmodel
is drawn only for two nearby conductor lines, first and ?th, for simplicity.
This modeling step corresponds to step 6 of Fig. 5. The model includes the
self-inductance (?), mutual capacitance between the first conductor line and
the ?th conductor line (?
) and via inductance of the package substrate
(a) Eight conductor lines in a circular conductor MLG used
Fig. 8(a) shows the entire schematic of the equivalent circuit
port and port 2 is the output port for the -parameter measure-
ment. Both ports are connected to the CPW of the substrates.
The remaining seven conductor lines of the MLG are connected
to the ground of the substrate. Fig. 8(b) shows the technique for
reducing the number of variables in the optimization process.
In determining the mutual inductance, we assumed that because
mutual inductance depends on the distance between two con-
ductor lines different weight factors must have existed for the
conductor lines with different distances. After calculating the
mutual inductance of the structure using Equation (1), we used
the weight factors to determine the mutual inductance value
in the optimization process 
the weight factors of the other conductor lines in the optimiza-
the height of the conductor andthe distance
lumped circuit model ?, ?, ? and ?. Port 1 (line 1) is connected to the CPW
on the package substrate and port 2 (line 1) is connected to the CPW of the
PCB substrate. The remaining conductor lines (2 to 8) were shorted to the low
impedance ground providing a current return path. (b) Relation between the
mutual inductance ?
and between the mutual capacitance ?
(a) Suggested equivalent circuit model of the test MLG based on the
tion process. The capacitance between the conductors is rep-
. The capacitance includes not only the mutual
capacitance between conductor lines but also the mutual capac-
itance of the vias. As shown in Fig. 8(b), the mutual capacitance
between the conductors is assumed to be inversely proportional
to the distance between them. Since the distances are known,
the mutual capacitance parameter is reduced to a single param-
, and the remaining six mutual capacitances
,, andare consequently determined using the
weight factors of the capacitances.
Fig. 9 shows the schematics of the circuits for the measure-
ment-based -parametersandconfiguration-based -parameters
that are used in the optimization. The measurement-based -pa-
rameters mean the -parameters obtained purely by measure-
ment, whereas the configuration-based -parameters mean the
-parameters obtained by simulation using the measured -pa-
rameters of the CPWs on the package substrate and PCB sub-
the configuration-based -parameters, we determined the pa-
rameter values using an optimization method. The parameters
to be determined were the inductance of the vias, the self induc-
AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL95
configuration-based ?-parameters that were used in the optimization. The
measurement-based ?-parameters mean the ?-parameters obtained purely by
measurement, and the configuration-based ?-parameters mean the ?-parameters
obtained by simulation using the measured ?-parameters of the CPWs on the
package substrate and PCB substrate.
Schematics of the circuits for measurement-based ?-parameters and
using the optimization method (step 6 of Fig. 5). The solid line represents
the ?-parameters from the measurement (step 3 of Fig. 5). The dotted line
represents the ?-parameters extracted on the basis of the suggested circuit
model and following optimization (step 7 of Fig. 5). The graphs are for the
MLG with an alumina dielectric of 0.3 mm height (h). (a) Comparison of the
magnitude and phase of ?
. (b) Comparison of the magnitude and phase of
Comparison of the ?-parameters after the parameter fitting process
tance and mutual inductance of conductor lines and the total ca-
pacitance of the conductor lines and vias. Fig. 10 shows the op-
timized -parameters of the equivalent circuit of the test vehicle
thatincludedtwoCPW linesandan MLGinterposer.Thereturn
) and the insertion loss (
phase form, are shown in Fig. 10(a) and (b), respectively. The
solid lines represent the configuration-based -parameters and
the dotted lines represent the measurement-based -parameters.
The left graph of the Fig. 10 represents the real parts of the pa-
), with the magnitude and
EXTRACTED MODEL PARAMETERS OF THE VARIOUS TYPES OF MLG BONDING
rameters and the right graph represents the imaginary parts of
the parameters. As shown in the Fig. 10, the parameters were
reasonably matched up to 20 GHz.
IV. VERIFICATION AND DISCUSSION
The extracted equivalent circuit model parameters of the var-
ious types of test MLG interposers are summarized in Table I.
means the self inductance of a conductor line,
means the mutual inductance between conductor line
1 and conductor line 2. The parameter
ductance of a via, and
of via 1 and via 2 of the MLG interposer. Since the inductance
of the MLG is strongly affected by the height of the MLG, the
inductance becomes smaller as the height decreases. For the
polymer MLG with a height of 0.2 mm, the self inductance is
120 pH, while for the ceramic MLG with a height of 0.4 mm,
the self inductance is 203 pH. As shown in Fig. 11(a), the in-
ductances are strongly dependent on, and proportional to, the
height of the MLG for both the polymer and ceramic insula-
tors. By reducing the height of the solder bump, the inductance
can be further reduced. The self inductance of the via in the
package substrate ranged from 81 pH to 102 pH, which is close
to previously reported values . The parasitic inductance in
the packages generates a simultaneous switching noise, as well
as a signal delay and reflections. Usually, to minimize the ef-
fect of the simultaneous switching noise of a high-speed dig-
ital system, a large portion of the I/O capability is used for
power/ground connections. Since the MLG has very little par-
asitic inductance, a larger number of the I/Os can be used for
other signal connections.
1 and the other seven metal lines (2, 3, 4, 5, 6, 7, and 8). Par-
asitic capacitances cause an additional delay and reflections in
high-speed digital signal transmission. In addition, mutual ca-
pacitance produces crosstalk voltages in nearby lines. The ca-
pacitance of the MLGA interposer, which has higher values be-
cause of the dielectric insulator between the conductor lines,
ranged from 175 fF to 312 fF. However, because of the low par-
asitic inductance, the resonance and cut-off frequencies were
means the self in-
means the mutual inductance
) is the sum
96 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003
MLG height on the capacitance of the MLG.
(a) Effect of MLG height on the inductance of the MLG. (b) Effect of
still above the millimeter range in the frequency spectrum. As
shown in Table I, the modeled capacitance for the same dielec-
tric insulator becomes smaller as the height of the conductor
line decreases. Consequently, reducing the MLG height reduces
the parasitic effects of the package and increases the operating
bandwidth. Another element that controls the parasitic effects is
the dielectric insulator that surrounds the conductor lines. Two
types of dielectric insulators were used: alumina (
and BT resin ( ). The capacitance of the MLGA inter-
poser with the alumina insulator was larger than the capacitance
of the MLGA interposer with the polymer insulator, as shown
in Fig. 11(b). When using the alumina insulator and with a
height of 0.5 mm,theMLGA interposerwith circularconductor
MLGs had a higher capacitance than the one with semi-cir-
cular conductor MLGs, as shown in Table I. The circular con-
consists of a time-domain reflectometer, cables, microprobes and a test vehicle
that includes a microstrip line and MLGA bonding.
Experimental setup for time-domain measurement using TDR. It
ductor lines, which are shown in Fig. 1(b), have a larger surface
area in contact with the alumina insulator, resulting in a larger
In the view of process variation, if there is 50 m of change
in distance between the nearest conductor lines, the capacitance
will change by 6.7%. In worst case, if there are changes of
50 m for all conductor lines distances due to the process vari-
ation, there will be 1.7% of the change in capacitance
In case of inductance, the mutual inductance between the con-
ductor lines will be affected by the change of the distance. As
the return current flows through the seven conductor lines and a
signal current will flow through a conductor line, the loop size
is directly affected by the distance between the lines. According
to the Equation (1), the mutual inductance change due to 50 m
of the process variation will be result in 5.3% change in
For verification of parameters from the extracted equivalent
circuit model, we measured time-domain signals using a
time-domain reflectometer, and we compared the measured
and simulated TDR/TDT waveforms. Fig. 12 shows the
experimental setup for the TDR/TDT measurement. Using a
vector network analyzer, we employed the same test vehicle
that was used for frequency-domain measurement. We used a
HP 54120B digital sampling oscilloscope and a 150
microprobe for this measurement. In Fig. 13, the simulated and
measured TDR/TDT waveforms are shown with an 80 ps rise
time for the source. In the TDR waveform, the inductance of
the vias, the capacitance of the vias and the MLG bonding as
well as the inductance of the MLGs are clearly observed in both
results of simulation and measurement. These results show a
very good correlation between simulation and measurement
Using the extracted model of Table I, we conducted some
simulations to characterize the effect of an MLG itself. The
insertion loss (
) of the MLG bonding was simulated in the
frequency domain. Fig. 14 shows the simulated insertion loss
of the MLG bonding for a height of 0.3 mm and an alumina
insulator. The insertion loss was 0.6 dB at 10 GHz, and 2.2 dB
AHN et al.: OVER GHz ELECTRICAL CIRCUIT MODEL97
domain. In the TDR waveform,inductance of the vias as well as the capacitance
and inductance of the MLGs are clearly observed in both results. The results
show a good correlation between simulated and measured waveforms.
TDR and TDT waveforms of simulation and measurement in a time
extracted model parameters (Table I) for a polymer MLG with a height (?) of
Simulated insertion loss (?
) of a single MLG bonding based on the
the MLG and the crosstalk noise at the nearby conductor line inside the MLG.
The simulation is based on the extracted equivalent circuit model parameters
(Table I) for the polymer MLG with a height (?) of 0.4 mm height.
Time-domain simulated waveforms of the transmitted signal through
at 20 GHz. Hence, the MLGA package is useful for microwave
device packages. Furthermore, the performance of the MLGA
package was simulated for high-speed digital device packages.
The simulated time-domain waveforms through the MLGA
bonding are shown in Fig. 15. The simulated MLG bonding
type and dimensions are the same as in Fig. 14. In the simula-
tion of the circuit operation, a digital pulse of 2 V peak-to-peak
voltage and a 30 ps rise time was applied to port 1 as an input
signal. The waveforms included the input pulse at port 1, the
transmitted pulse at port 2, the near-end crosstalk at conductor
line 2 and the far-end crosstalk at conductor line 2. The output
signal had a 0.103 V overshoot, 0.197 V near-end crosstalk and
0.069 V far-end crosstalk noise. This simulation shows that
MLG bonding can be used for digital device packages of more
than 5 GHz clock frequency and with a 30 ps rise time.
We developed a high-frequency equivalent circuit model of
an MLGA interposer. The model was derived on the basis of
-parameter measurements and subsequent microwave network
analysis.Toconduct accuratemicrowavemeasurementsand de-
rive reliable model parameters, the test MLGA devices were
carefully designed and tested using a vector network analyzer
and TDR. We measured several types of MLG interposers with
different dielectric insulators and dimensions. Circuit simula-
tion based on the extracted model reveals that the MLGA in-
terposer can be used for millimeter microwave device packages
with operating frequencies of more than 20 GHz and for digital
device packages with clock cycles faster than 5 GHz. Although
eight conductor lines were embedded in each MLG, more con-
ductor lines could be implemented to enable the MLGs to func-
tion as very high density, high-I/O packages.
Reducing the height of the MLG has been shown to decrease
the effects of parasitic inductance and capacitance. To further
reduce the parasitic inductance and capacitance of the MLGA
package and, hence, to increase the frequency range of the ap-
plications, the height of the solder bump should be reduced. Re-
ducing the height of the MLGA interposer and the solder bump
erties. The electrical performance requires a compromise with
the mechanical and thermal requirements. The parasitic capac-
itance of the MLG bonding between the conductor lines can
be reduced by using different insulators with smaller dielectric
constants. A unique feature of the MLGA interposer is the im-
plementation of passive devices inside the MLGA substrate. In
particular, byusing amultilayer process,itemssuchasresistors,
embedded capacitors, inductors and filters can be merged into
the MLGA structure. Further study on the design of these pas-
sive devices and their characterization is necessary to enhance
the application of the MLGA interposer.
 M. P. R. Panicker et al., “Ball grid arrays: A DC to 31.5 GHz low cost
packaging solution for microwave and MM-wave MMICS,” Microwave
J., vol. 41, no. 1, pp. 158–168, Jan. 1998.
 Y. S. Kim and C. K. Yoon, “Multiple line grid array (MLGA) package,”
in Proc. Int. Conf. High-Density Interconnect Syst. Packag., May 2000,
 J. Lee, S. Ahn, S. Baek, and J. Kim, “Design and estimation of em-
bedded passives in multiple line grid array (MLGA) package,” in Proc.
Int. Symp. Electron. Mater. Packag., Nov. 2000, pp. 340–345.
 T. Chang, P. H. Cheng, H. C. Huang, R. S. Lee, and R. Lo, “Parasitic
characteristics of BGA packages,” in Proc. IEEE Symp. IC/Package De-
sign Integr., 1998, pp. 124–129.
98 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 26, NO. 1, FEBRUARY 2003 Download full-text
 C. Mattei and A. P. Agrawal, “Electrical characterization of BGA pack-
ages,” in Proc. 47th Electron. Comp. Technol. Conf., May 1997, pp.
 W. Ryu, M.-J. Yim, S. Ahn, J. Lee, W. Kim, K.-W. Paik, and J. Kim,
“High-frequency SPICE model of anistropic conductive film flip-chip
interconnections based on a genetic algorithm,” IEEE Trans. Comp.
Packag. Technol., vol. 23, pp. 542–545, Sept. 2000.
 W. Ryu, M.-J. Yim, J. Lee, Y.-D. Jeon, S. Ahn, W. Kim, K.-W. Paik, and
J. Kim, “Microwave model of flip-chip interconnects using anisotropic
conductive film,” in Proc. Int. Conf. High Density Packag. MCM, 1999,
 S. Ahn, W. Ryu, M.-J. Yim, J. Lee, Y.-D. Jeon, W. Kim, K.-W. Paik,
and J. Kim, “Over 10 GHz equivalent circuit model of ACF flip-chip
interconnect using Ni-filled ball and Au-coated polymer balls,” in Proc.
24th Int. Electron. Manufact. Technol. Symp., Oct. 1999, pp. 421–425.
 F. W. Grover, Inductance Calculations—Working Formulas and
Tables. New York: D.Van Nostrand, 1946.
 H. H. M. Ghouz and EL-Badawy EL-sharawy, “An accurate equivalent
Theory Tech., vol. 44, pp. 2543–2553, Dec. 1996.
Seungyoung Ahn received the B.S. and M.S. degrees in electrical engineering
from the Korea Advanced Institute of Science and Technology (KAIST),
Daejeon, in 1998 and 2000, respectively, where he is currently pursuing the
From 2001 to 2002, he was a Visiting Researcher in the Elecronics Pack-
aging Group, Singapore Institute of Manufacturing Technology, Singapore. His
current research interests include modeling and design of high-speed intercon-
nection and package for GHz signaling.
Junho Lee received the B.S. degree in radio science and communication
engineering from Hong-ik University, Seoul, Korea, in 1998, and the M.S.
degree in electrical engineering from the Korea Advanced Institute of Science
and Technology (KAIST), Taejon, in 2001, where he is currently pursuing the
His current research interests are high speed digital interconnect modeling
and high frequency power/ground modeling.
Junwoo Lee received the B.S. and M.S. degrees in electrical engineering from
the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in
1999 and 2001, respectively, where he is currently pursuing the Ph.D. degree.
Since April 2002, he has worked at the Institute of Microelectronics, Sin-
gapore, as a one-year intern. His current research interest is in the design and
modeling of high frequency package interconnections and power distribution
Jonghoon Kim (S’97) received the B.S. degree in electronics from Yeungnam
University, Daegu, Korea, in 1995 and the M.S. degrees in electrical en-
gineering from the Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, in 1998 where he is currently pursuing the Ph.D. degree in
the reduction of electromagnetic interference (EMI) from high-speed digital
Woonghwan Ryu received the B.S. degree in computer engineering from
Kwangwoon University, Seoul, Korea, in 1994, and the M.S. and Ph.D. degrees
in electrical engineering from the Korea Advanced Institute of Science and
Technology (KAIST), in Daejeon, in 1997 and 2001, respectively.
From 2000 to 2001, he was a Visiting Researcher in the Electronics Pack-
aging Group, Gintic Institute of Manufacturing Technology, Singapore. From
1997 to 2001, he was under educational program as an Associate Engineer at
Samsung Electronics Co., Ltd. In 2001, he joined the Signal Integrity Engi-
neering Group, Intel Corporation, where he is currently a Staff Signal Integrity
Engineer. He is now working on signal/power integrity analysis in Intel Chipset
DDR-I/II/III memory interface, high-frequency EM modeling, and broadband
device characterization. In addition, he is currently leading the Frequency-Do-
main (FD) Working Group to develop high-frequency FD methodologies in-
cluding topology optimization, EM modeling, and GHz VNA characterization.
He has been working with GHz system signal integrity analysis, high-speed
VLSI interconnection, microwave package modeling, RF circuit design, and
over GHz and low-power clock distribution, especially RF clock distribution.
He has authored and co-authored more than 50 technical publications including
four pending patents, journals, and conference proceeding papers.
Byung-Hun Kum received the B.S. and M.S. degrees in material engineering
from the University of Myongji, Youngin, Korea.
He is a Process Engineer for Glotech, Inc., Seoul, Korea, wherehe researches
multiple line grid array (MLGA) technology for application of the advanced
electronic packaging and smart connector.
Hyun-Seok Choi received the B.E. and M.E. degrees in ceramic engineering
from Yonsei University, Seoul, Korea, in 1996 and 1998, respectively.
He was a Student Researcher with the Thin-Film Technology Research
Center, Korea Institute of Science and Technology (KIST), taking a univer-
sity-KIST collaborative graduate course from 1996 to 1998. He joined the IC
Package Team, Glotech, Inc., Seoul, in 1999. He is currently a Researcher
engaged in the development of the multiple line grid array (MLGA) package
Chong K. Yoon received the B.A. and M.A. degrees in metallurgy from Yonsei
University, Seoul, Korea, in 1976 and 1979, respectively, and the Ph.D. degree
in materials science from the University of Michigan, Ann Arbor, in 1990.
He is a CEO at Glotech, Inc., Seoul, and working on proliferation of the
fields of interest are interconnections in packages and connectors, especially fo-
cusing on design, materials selection, and characterization.
Dr. Yoon is a member of IMAPS.
Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and
the Ph.D. degree in electrical engineering from the University of Michigan,
Ann Arbor, in 1993. His doctoral thesis was study on the femtosecond time-
domain optical measurement techniques for the testing of high-speed digital
devices and millimeter-wave circuits.
After receiving the Ph.D. degree, he moved to Picometrix, Inc., Ann Arbor,
in 1993, to work as a Research Engineer, where he was responsible for the de-
velopment of a picosecond sampling system and a 70-GHz photo-receiver. In
1994, he joined the Memory Division, Samsung Electronics, Kiheung, Korea,
where he was engaged in a 1-Gb DRAM design. In 1996, He moved to the
Korea Advanced Institute of Science and Technology (KAIST), Taejon. He is
currently an Associate Professor with the Electrical Engineering and Computer
Science Department. Since joining KAIST, his research interest centers on the
modeling, the design and the testing of high-speed interconnections, packages,
PCB, and connectors over GHz frequency range. Related research topics are
signal integrity, crosstalk, SSN, and EMI problems. He was on sabbatical leave
during the academic year from 2001 to 2002 at Silicon Image, Inc., Sunnyvale
CA, as a Staff Engineer. He has authored or co-authored over 100 technical ar-
ticles and numerous patents.