High-Q on-chip inductors using extremely thick silicon dioxide and copper-damascene technology

Abstract

High performance on-chip inductors fabricated using extremely thick low-stress silicon dioxide (SiO₂) as the interface layer and copper damascene technology on standard CMOS silicon substrate are presented. A warpage-free low-stress SiO₂ layer up to 20 mum thick is deposited using a modified deposition process. The maximum quality factor of a 1.3 nH inductor has been improved by 160% (from 21 to 55) when the thickness of SiO₂ increases from 0.3 to 15 mum.

Full text

Page 1

Copyright © 2008 Year IEEE. Reprinted from ELECTRONICS LETTERS 31st January
2008 Vol. 44 No. 3. Such permission of the IEEE does not in any way imply IEEE
endorsement of any of Institute of Microelectronics’ products or services. Internal or
personal use of this material is permitted. However, permission to reprint/republish this
material for advertising or promotional purposes or for creating new collective works for
resale or redistribution must be obtained from the IEEE by writing to pubs-
permission@ieee.org.

Page 2

High-Q on-chip inductors using extremely
thick silicon dioxide and copper-damascene
technology
M. Tang, H.Y. Li, Q.X. Zhang, E.B. Liao, A.B. Yu, G.Q. Lo,
N. Balasubramanian and D.L. Kwong
High performance on-chip inductors fabricated using extremely thick
low-stress silicon dioxide (SiO2) as the interface layer and copper
damascene technology on standard CMOS silicon substrate are pre-
sented. A warpage-free low-stress SiO2layer up to 20 mm thick is
deposited using a modified deposition process. The maximum
quality factor of a 1.3 nH inductor has been improved by 160%
(from 21 to 55) when the thickness of SiO2increases from 0.3 to
15 mm.
Introduction: On-chip spiral inductors are widely used in silicon radio-
frequency integrated circuits (RFICs) as a system-on-chip solution [1].
The performances of on-chip inductors are severely limited by the
lossy silicon substrate. One solution is post-processes, such as silicon
substrate thinning and removal, to achieve high-Q high-frequency per-
formance [2, 3]. However, they have disadvantages of weak mechanical
strength and a heavy self-heating effect [4]. The alternative solution is to
insert athick low-loss dielectric layer between the inductor metal and the
lossy silicon substrate, such as polyimide, benzocyclobutene (BCB) and
silicon dioxide (SiO2). In [5, 6], transformers and inductors on localised
thick SiO2layers with improved performance were demonstrated, where
20 mm-thick SiO2layers were fabricated using deep reactive ion etching
(DRIE) with subsequent thermal oxidation, SiO2refill and chemical
mechanical polishing (CMP). In this Letter, we present a simple fabrica-
tion technology for high-performance on-chip inductors on a thick SiO2
layer, where SiO2up to 20 mm thick is deposited using a modified
PECVD process and the wafer keeps warpage-free.
Fig. 1 Cross-sectional view and microphoto of two-turn inductor
a Cross-sectional view
Spiral coil built using 2.5 mm-thick M2 Cu layer; underpass built using 1 mm-
thick M1 Cu layer. M3 is Al layer for test pads and via layer is 0.8 mm-thick Cu
b Microphoto
Fabrication process: Circular spiral inductors were fabricated using
0.13 mm CMOS back end technology with three copper (Cu) layers
and low-stress SiO2 as inter-metal dielectric (IMD) on a CMOS
p-type silicon substrate. A cross-section schematic and a SEM micro-
photo of a two-turn circular inductor are shown in Figs. 1a and b,
respectively. The fabrication process started with deposition of a thick
low-stress silicon dioxide film on the silicon substrate at 3508C using
the standard Novellus PECVD machine. The challenge for the normal
PECVD SiO2deposition process is that the wafer warpage increases
with the deposition thickness rapidly owing to increasing stress of the
SiO2 layer. The wafer warpage is about 230 mm (centre to edge
displacement) when 20 mm-thick SiO2is deposited using the standard
PECVD process (SiH4/N2O as precursors), as shown in Fig. 2a. The
large wafer warpage may cause wafer broken or E-chuck failure
during loading/unloading steps of the subsequent processes. It is
found that adding nitrogen into the layer can reduce the film stress
and the wafer warpage effectively. The key lies in the ratio of the chemi-
cal precursors (SiH4/N2O/N2) used in the PECVD process to achieve
warpage-free low-stress SiO2 film. Fig. 2a shows that the wafer
warpage decreases with an increase of the nitrogen ratio in the gas
mixture. The wafer warpage is reduced to 20.7 mm for 20 mm-thick
SiO2deposited using recipe 3, which is flat enough for the subsequent
inductor processes. The deposition rate is typically ?63 nm/s. Fig. 2b
shows that the wafer warpage increases from 9.4 to 20.7 mm when
SiO2thickness increases from 5 to 20 mm deposited using the optimised
PECVD process.
Fig. 2 Measured wafer warpage for 20 mm-thick SiO2 deposition with
increasing N2 content in PECVD gas mixture and measured wafer
warpage with SiO2thickness deposited using optimised PECVD process
a 20 mm-thick SiO2deposition with increasing N2content in PECVD gas mixture
b SiO2thickness deposited using optimised PECVD process
The Cu-damascene process was implemented three times to form M1,
via and M2 layers on the thick SiO2interface layer. All inter-metal
dielectric layers are low-stress SiO2too. The bottom metal layer M1 is
1 mm thick, used for the underpass. The via layer is 0.8 mm thick.
The metal layer M2 is 2.5 mm thick, used for the spiral coils. Next,
300 nm SiO2was deposited to protect the M2 surface. After opening
the test pads area by etching the top SiO2, M3–0.75 mm aluminium
was sputtered and patterned as test pads.
Results and discussion: Two- to seven-turn circular spiral inductors
ranging from 1.3 to 11.5 nH were designed and fabricated. The line
width, w, is 12 mm, the line space, s, is 1.4 mm and the inner diameter,
Din, is 100 mm. The pads’ shunt parasitics of the test structures were
de-embedded using open calibration structures fabricated next to the
device under test (DUT). The inductance, L, and the quality factor, Q,
oftheinductor were thenextracted
Y-parameters based on L ¼ Im(1/Y11)/(2pf ) and Q ¼ Im(1/Y11)/
Re(1/Y11), where f is the frequency.
from thede-embedded
ELECTRONICS LETTERS 31st January 2008Vol. 44No. 3

Page 3

The inductance and the quality factor of a 2.4 nH three-turn inductor
with SiO2thickness are compared in Fig. 3. When the thickness of SiO2
increases from 0.3 to 15 mm, the inductance at low frequencies shows
little change. However, the resonant frequency increases from 16.75 to
18.9 GHz. The maximum quality factor of the inductor has been
improved by 242%, from 12.6 at 2.25 GHz to 43.1 at 6.9 GHz. The
thick SiO2reduces the field coupling between the inductor and the
silicon substrate. Therefore, the loss associated with eddy currents
generated in the silicon substrate decreases. The frequency at which
the substrate loss becomes significant also increases, resulting in a
higher quality factor and a higher resonant frequency.
Fig. 3 Inductance and quality factor of inductor with different SiO2thickness
h (N ¼ 3)
Fig. 4 plots the maximum quality factor of inductors against
inductance when the thickness of SiO2increases. It shows dramatic
improvement of the maximum quality factors of inductors with the
thickness of SiO2, and such improvement is more significant for induc-
tors with smaller inductance, i.e. less number of turns. For example, the
maximum quality factor of 1.3 nH inductor is improved by 160% from
21 to 55 when the thickness of SiO2increases from 0.3 to 15 mm.
Fig. 4 Maximum quality factor of inductors, change with different SiO2
thickness h (N ¼ 2–7)
Conclusions: High-Q inductors employing a thick SiO2 dielectric
interface layer have been demonstrated on the standard CMOS silicon
substrate. By using a modified PECVD deposition process, warpage-
free low-stress SiO2with a thickness up to 20 mm has been deposited
as the interface layer to suppress the substrate loss. A maximum
quality factor of 43.1 is achieved at 6.9 GHz for a 2.4 nH inductor.
This CMOS compatible approach for fabricating high-Q inductors is
suitable for single-chip implementation of RFICs.
# The Institution of Engineering and Technology 2008
18 October 2007
Electronics Letters online no: 20083010
doi: 10.1049/el:20083010
M. Tang, H.Y. Li, Q.X. Zhang, E.B. Liao, A.B. Yu, G.Q. Lo,
N. Balasubramanian and D.L. Kwong (Institute of Microelectronics,
11 Science Park Road, 117685 Singapore)
E-mail: tangm@ime.a-star.edu.sg
References
1Lee, T.H.: ‘The design of CMOS radio-frequency integrated circuits’
(Cambridge University Press, UK, 1998)
Ng, K.T., Rejaei, B., and Burghartz, J.N.: ‘Substrate effects in monolithic
RF transformers on silicon’, IEEE Trans. Microw. Theory Tech., 2002,
50, (1), pp. 377–383
Lakdawala, H., Zhu, X., Luo, H., Santhanam, S., Carley, L.R., and
Fedder, G.K.: ‘Micromachined high-Q inductors in a 0.18-mm copper
interconnect low-K dielectric CMOS process’, IEEE J. Solid-State
Circuits, 2002, 37, (3), pp. 394–403
Sagkol, H., Sinaga, S., Burghartz, J.N., Rejaei, B., and Akhnoukh, A.:
‘Thermal effects in suspended RF spiral inductors’, IEEE Electron
Devices Lett., 2005, 26, (8), pp. 541–543
Jiang, H., and Tien, N.C.: ‘Monolithic transformer with underlying deep
silicon-oxide block’, Electron. Lett., 2002, 38, (3), pp. 142–144
Sun, J., and Miao, J.: ‘High performance MEMS inductors fabricated on
localised and planar thick SiO2layer’, Electron. Lett., 2005, 41, (7),
pp. 446–447
2
3
4
5
6
ELECTRONICS LETTERS31st January 2008 Vol. 44No. 3