Interface state generation during electrical stress in n-channel undoped hydrogenated polysilicon thin-film transistors

Bulgarian Academy of Sciences, Ulpia Serdica, Sofia-Capital, Bulgaria
Electronics Letters (Impact Factor: 0.93). 12/1998; 34(24):2356 - 2357. DOI: 10.1049/el:19981616
Source: IEEE Xplore


Interface state generation effects due to hot carrier phenomena
are studied in n-channel undoped hydrogenated polysilicon thin-film
transistors under on-current bias-stress conditions. At the initial
stages of stressing, interface states are created as well as hot hole
trapping. As the stress process proceeds further, a saturation of the
density of generated interface states was found after which hot electron
injection into the gate oxide becomes the most important factor in
further device degradation

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    • "Reliability is one of the major concerns , especially when a device is operated under high drain and high gate voltages. Hot carrier stress under high drain and high gate voltages decreases the transconductance, turn-on current, sub-threshold slope and increases the threshold voltage [1], [2]. Although the study of device aging with stress time under static hot-carrier stress has been systematically reported [3], to our knowledge, a study of the degradation in poly-Si TFT performance under dynamic hot-carrier stress has not been reported. "
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    ABSTRACT: We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G/sub m max/) in static stress, G/sub m max/ in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation.
    IEEE Electron Device Letters 11/2001; 22(10-22):475 - 477. DOI:10.1109/55.954916 · 2.75 Impact Factor
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    ABSTRACT: We applied hot carrier stress in excimer laser annealed n-channel polycrystalline thin film transistors (polysilicon TFTs) with large grain size. Two diff erent modes of degradation were observed for electrically identical devices: one' rapid and efficient and another almost negligible degradation. We believe that hot carrier stress in polysilicon TFTs is strongly dependent on structural nonĀ­ uniformity. Leakage current measurements as well as analytical studies were performed in order to identify the mechanisms responsible for the device degradation.
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    ABSTRACT: Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.
    Microelectronics Reliability 06/1999; 39(6):885-889. DOI:10.1016/S0026-2714(99)00118-3 · 1.43 Impact Factor
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