A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems
ABSTRACT In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.
Conference Proceeding: Combinational Logic Soft Error Correction[show abstract] [hide abstract]
ABSTRACT: We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniquesTest Conference, 2006. ITC '06. IEEE International; 11/2006
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ABSTRACT: A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm<sup>2 </sup>/mg) at V<sub>DD</sub>=1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are describedIEEE Transactions on Nuclear Science 01/2007; · 1.22 Impact Factor
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ABSTRACT: This paper presents a study using alpha- and neutron-accelerated tests to characterize the soft error rate (SER) of flip-flops (FFs) that are used in 90-nm CMOS production designs. The investigated FFs differ in circuit schematic, threshold voltage (V<sub>T</sub>), drive strength, and cell height. Both the alpha- and the neutron-induced SER of FFs on a dedicated 90-nm test chip showed a strong dependence on clock and data state. Theoretical results demonstrate that the FF SER is modeled best if particle hits at both the NMOS and the PMOS drains are included and if the resulting current pulse is assumed to have a width of approximately 5 ps. Furthermore, the impact of process variations on the FF SER is shown to depend strongly on the data state and on the applied pulsewidth. On average, the SER per bit of the investigated FFs is higher than the typical SER per bit of unprotected static random access memories in 90 nm and has increased with a factor of 3 per technology generation. The reported results illustrate the importance of the characterization of FF SER in order to design reliable integrated circuits.IEEE Transactions on Device and Materials Reliability 04/2007; · 1.52 Impact Factor