Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

ETH Zurich, Zurich
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 08/2008; 16(7):830 - 836. DOI: 10.1109/TVLSI.2008.2000457
Source: IEEE Xplore


Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V dd-to-ground paths also contributes to a significant decrease of static consumption.

1 Follower
119 Reads
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an 8×8bit pipelined multiplier operating at 320MHz under 0.5V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5V. The proposed pipelined multiplier is fabricated in 130nm CMOS process. It operates up to 320MHz and the power consumption is only 1.48mW at 0.5V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5V is reduced over 5.7 times than that of the traditional architecture at 1.2V. Thus, the proposed 8×8bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.
    Microelectronics Journal 01/2011; 42(1):43-51. DOI:10.1016/j.mejo.2010.09.005 · 0.84 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic dependency on chain-length. This necessitates buffer insertion at depth 3 or 4 for chain of transmission gate in the current analysis methodology. In this paper, the dependency on two more factors such as fan-out and input-pattern are discussed. We show that the delay is dynamic and exponential depending on input-pattern and fan-out respectively. As a consequence, the insertion of buffer at proper depth is necessary for different fan-out configuration. A restoring mode transmission gate (RMTG) XOR gate is proposed which shows little dependency on fan-out and input patterns thereby eliminate the complexity of buffer insertion. The Spice simulation in 180nM UMC Technology shows that our proposed RMTG XOR is 13.21% and 31.34% faster, 51.63% and 1.72% power efficient compared to the conventional CMOS XOR and TG XOR respectively for a load capacitance of 10 fF. Our proposed model consumes less hardware compared to the conventional CMOS XOR.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Abstract—In this work, we designed a 10 transistor full adder for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies 90nm, 70nm, 50nm. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. Two Components contribute to the power dissipation in CMOS circuits. The Static dissipation is due to leakage current, while dynamic power dissipation is due to switching transient current as well as charging and discharging of load capacitances.
    Proceedings of the IEEE 04/2011; DOI:10.1109/ICECTECH.2011.5941755 · 4.93 Impact Factor
Show more