Write Disturbance Modeling and Testing for MRAM

Abstract

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 3, MARCH 2008277
Write Disturbance Modeling and Testing for MRAM
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang,
Yuan-Jen Lee, and Ming-Jer Kao
Abstract—The magnetic random access memory (MRAM) is
considered one of thepotential candidates thatwill replace current
on-chip memories (RAM, EEPROM, and flash memory) in the
future. The MRAM is fast and does not need a high supply voltage
for read/write operations, and is compatible with the CMOS
technology. It can also endure almost unlimited read/write cycles.
These combined advantages of RAM and flash memory make it
a potential choice for SOC. In this paper, we present the write
disturbance fault (WDF) model for MRAM, i.e., a fault that affects
the data stored in the MRAM cells due to excessive magnetic field
during the write operation. We also construct the SPICE macro
model for the magnetic tunneling junction (MTJ) device of the
toggle MRAM to obtain circuit simulationresults. We thenpresent
an MRAM fault simulator called RAMSES-M, based on which
we derive the shortest test for the proposed WDF model. The
test is shown to be better and more robust as compared with the
conventional March C- test algorithm. We also present a March
17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM
chip has been designed and fabricated using a CMOS-based
0.18- m technology. The proposed WDF model is justified by chip
measurement results, with the march test results reported. Finally,
specific MRAM fault behavior and test issues are discussed.
Index Terms—Failure analysis, fault model, fault simulation,
magnetic random access memory (MRAM), memory testing,
nonvolatile memory, write disturbance fault (WDF).
I. INTRODUCTION
W
and capacity) in system-on-chip (SOC) designs is growing
rapidly. According to the recent ITRS report [1], memory cores
represent a significant portion of a typical SOC and dominate
the chip yield. Many applications require the chips to integrate
nonvolatile memories. Although flash memory is widely used
today,itsuffersfromproblemssuchashighvoltageforprogram
and erase operations and reliability issues [2]. The industry
has been trying to find a new nonvolatile memory to replace
flash memory. Possible candidates include magnetic random
access memory (MRAM), ferroelectric random access memory
ITH TODAY’S advanced deep-submicrometer process
technologies,theuseofmemorycores(intermsofcount
Manuscript received February 28, 2007; revised April 30, 2007.
C.-L. Su and C.-W. Wu are with the Department of Electrical Engineering,
National Tsing Hua University, Hsinchu 30013, Taiwan, R.O.C. (e-mail:
clsu@larc.ee.nthu.edu.tw).
C.-W. Tsai is with the R&D Department, Skymedi Corporation, Hsinchu,
30013 Taiwan, R.O.C.
C.-C. Hung, Y.-S. Chen, D.-Y. Wang, and M.-J. Kao are with the Depart-
ment of Non-Volatile Memory Technology, Electronics Research and Service
Organization(ERSO)/IndustrialTechnologyResearchInstitute(ITRI),Hsinchu
30013, Taiwan.
Y.-J. Le is with the Nanoelectronic Device Technology Division, Electronics
ResearchandServiceOrganization(ERSO)/IndustrialTechnologyResearchIn-
stitute (ITRI), Hsinchu 30013, Taiwan.
Digital Object Identifier 10.1109/TVLSI.2007.915402
(FeRAM), Ovonic universal memory (OUM), etc. Among
them, MRAM has the advantages of high speed, high density,
low power consumption, and almost unlimited read/write en-
durance. The data storing/switching mechanism of MRAM is
based on the resistance change of the magnetic tunnel junction
(MTJ) device in each cell. The MTJ device of an asteroid
MRAM is made of tunneling magnetoresistive material (TMR)
[3]–[6]. Unfortunately, asteroid MRAM devices face problems
such as the disturbance by half-selected cells and loss of data
due to thermal agitation [7], [8]. The toggle MRAM has been
proposed to solve that issue [9], and several toggle MRAM
designs have been reported recently [8], [10]–[12]. In general,
compared with asteroid MRAM, the toggle MRAM has better
write and read margins, higher reliability, better scalability, etc.
However, that does not mean the reliability and test issues are
solved [13].
In this paper, we address some testing issues of toggle
MRAM. We begin with the fault models, which are used
for subsequent testing and diagnostics of the MRAM chips.
There have been many research works on RAM fault models
published in the past (see [14] for a summary of conventional
RAM fault models). With proper fault models, test algorithm
generation can be greatly simplified [15]. In [16]–[20], several
flash memory testing approaches have been presented, in which
disturbance fault models and their test algorithms are proposed.
In [15] and [19], fault simulators for RAM and flash memory
are presented, which are used to evaluate the fault coverage of
test algorithms and even to generate efficient test algorithms
for ever-changing RAM and flash products. In our previous
work [21], we perform MRAM defect analysis based on the
SPICE model for an MTJ made of TMR. In this paper, that is
an extended version of [22], we further provide chip measure-
ment results to show the existence of write disturbance fault
(WDF) model. We propose the WDF model for toggle MRAM,
which is a fault that affects the data stored in the MRAM cells
due to excessive magnetic field during the write operation
MTJ cell operating region. Based on that, we also develop the
corresponding MTJ SPICE model. In addition, we present an
MRAM fault simulator called RAMSES-M, which is used to
derive the shortest test for WDF, and a March 17 N diagnosis
algorithm for identifying WDF. A 1-Mb MRAM chip has
been designed and fabricated using a CMOS-based 0.18- m
technology. The MRAM die photo is shown in Fig. 1. Again,
the MRAM chip measurement results show the existence of
WDF. We discuss the test results obtained from the March C-
and March 17 N test algorithms. Finally, a specific MRAM
fault and the related test issues are discussed.
The rest of this paper is organized as follows. Section II in-
troduces the basic structure of MRAM and some characteristics
of the toggle MTJ cell. The WDF model for toggle MRAM is
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278IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 3, MARCH 2008
Fig. 1. Die photo of the 1-Mb toggle MRAM.
Fig. 2. Typical structure of a 1T1MTJ MRAM cell.
described in Section III. In Section IV, the toggle MRAM cir-
cuit model is introduced. Section V summarizes the simulation
results of our proposed device model and memory fault simu-
lator (RAMSES-M).The MRAMchipmeasurementresults and
discussionofaspecificMRAMfaultaregiveninSectionVI.Fi-
nally, Section VII concludes this paper.
II. MRAM
A typical one-transistor-one-MTJ (1T1MTJ) cell is used
in both the asteroid MRAM and toggle MRAM. The toggle
MRAM differs from the asteroid MRAM in the MTJ material
stack and write mechanism.
A. MRAM Material
A typical 1T1MTJ cell structure is shown in Fig. 2. The bit-
line (BL) is on top of the MTJ, and the write word-line (WWL)
is under the MTJ. There are currents going through these two
operating wires to generate perpendicular magnetic fields, for
storing data into the MTJ devices during the write operation.
The read word-line (RWL) controls the MOS transistor (as a
switch) toactivate the read operation. The MTJ logic state is de-
termined by the corresponding magnetic state. During the read
operation, the output data is determined by comparing the MTJ
current with the reference current
by the sense amplifier.
Fig. 3. MTJ material layers of the toggle MRAM cell.
Fig. 4. Phased write pulse sequence of toggle MRAM.
The MTJ material layers for toggle MRAM are shown in
Fig.3,whichcanroughlybepartitionedintothreelayers:1)free
synthetic antiferromagnet (SA) layer; 2) tunnel barrier layer;
and 3) pinned SA layer. The two SA layers are, respectively,
connected to the top and bottom electrodes, which are in turn
connected to the pass transistor and the sense amplifier, respec-
tively (see Fig. 2). The free SA layer is composed of two fer-
romagnetic (NiFe) sub-layers separated by a coupling spacer
(Ru) layer, which exhibits opposite magnetization. The major
difference between the MTJ material in toggle MRAM and that
in asteroid MRAM is the free SA layer—it is changed from a
single ferromagnetic (NiFe/CoFe) layer to the synthetic antifer-
romagnet(NiFe/Ru/NiFe)layer.TheCoFe/Ru/CoFepinnedSA
layer is used to provide fixed magnetic moment for the free SA
layer. As a result of the use of the free SA layer, the magnetic
easy and hard axes are oriented
and WWL, respectively [8].
45 with respect to the BL
B. MRAM Operation
As opposed to the asteroid MRAM, the write operation of the
toggle MRAM is divided into four write pulse phases called the
Savtchenko switching [9]. We use the sequence of write pulse
phases to program the MTJ device with the magnetic fields gen-
erated by the BL and WWL currents in different phases, as
shown in Fig. 4 [23]. The arrows
the magnetic moments of free sub-layer 1, free sub-layer 2, and
fixedlayerinFig.3,respectively.InFig.3,
the fields generated by the currents on WWL and BL, respec-
tively. The dashed arrow is the vector sum of
in a asteroid MRAM, the logic state of a toggle MRAM cell is
determined by the relationship between the magnetic moments
of the free layer and pinned layer, i.e.,
,, andrepresent
andstandfor
and. As
and . A par-
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SU et al.: WRITE DISTURBANCE MODELING AND TESTING FOR MRAM279
Fig. 5. Operating regions of toggle MRAM.
allelalignmentof
(logic 0)—see Phase t0 of Fig. 4. Phase t4 in Fig. 4 shows the
high-resistance state (logic 1), which is done by an anti-parallel
alignment between
and
shows the bit transition from logic 0 to 1. The reversed transi-
tion—from 1 to 0—can be completed by the same write pulse
sequence. The magnetoresistance ratio (MR) is the ratio of the
difference of the resistance values in parallel state (low resis-
tance) and anti-parallel state (high resistance) to the resistance
value in parallel state. It can be represented as
andresultsinthelow-resistancestate
. The phase sequence in Fig. 4
(1)
The resistances of the two states are denoted as the anti-parallel
orientation resistance
and parallel orientation resistance
, respectively.
Both rising and falling transitions are done by the same
toggle sequence, so the toggle MRAM needs a read-be-
fore-write mechanism to determine the original bit stored
in the MTJ device. During the write operation, the applied
field should be large enough to toggle the data bit stored in
the MTJ device. Fig. 5 depicts the operating regions of the
toggle MRAM cell. When the total magnetic field is in any of
the two light shaded regions (marked Toggling), the data bit
in the MTJ device is toggled successfully. When it is in the
no-switching area, the data bit will not change. If, however, it is
in a dark shaded region, the data bit will become unknown. The
operating regions of toggle MRAM is apparently larger than
asteroid MRAM, and half-selected cells will not suffer from the
disturbance of external single field. Moreover, toggle MRAM
has the advantages of reduced overall power consumption and
smaller transistor (due to unidirectional currents) [8], [24].
III. MRAM FAULT MODELS
A. Magnetic Field Impact on MRAM Operations
During the write operation, currents are applied to WWL
and BL to change the data stored in the MRAM. The currents
generate magnetic fields to change the state of the MTJ device.
As discussed previously, writing is done by a sequence of
Fig. 6. Magnetic field generated by a current on BL.
four write pulse phases that toggle the MTJ device. In each
phase there is a unique combined magnetic field generated by
the currents. We use
to represent the magnetic field sequence on the base cell (cell
being operated) with respect to the phase sequence, where
anddenote the magnetic fields of the base cell
generated by currents on WWL (row) and BL (column),
respectively. Although the currents are only applied to
WWL and BL of the base cell, all cells in the memory
array are affected by the magnetic field they generate during
the write operation. We define the field sequence function
as
the magnetic field sequence on any MTJ cell during the write
operation, where
and are coefficients specific to the target
MTJ cell (relative to those of the base cell). During the MRAM
write operation,
andof the base cell are equal to 1, and
those of other cells are less than 1. In Fig. 6, we illustrate the
magnetic field generated by a current on BL, assuming that
the BL current flows away from the eyes. From Ampere’s
right-hand rule, the direction of the magnetic field is clockwise.
As shown in Fig. 6, the magnetic field affects all cells, except
that the strength varies. A current on a WL has a similar effect.
Although every MTJ cell is influenced by the magnetic field,
the strength is dependent on its distance to the active BL and
WL. From the Biot–Savart law, the magnetic field of the base
cell can be expressed as
denote the permeability of free space, current on the wire, and
distance between the MTJ device and the wire. To increase the
efficiency of magnetic field, we put BL on top of the MTJ de-
vice, and WWL is under the MTJ device. Note that we only
consider the MTJ cells controlled by the same WWL here. In
Fig. 6,
is the thickness between the BL layer and MTJ layer,
and
is the distance between adjacent MTJ devices. During
the write operation, the magnetic field generated by BL current
of base cell is
BL current of base cell on an adjacent MTJ cell can be repre-
sented as
, where, , and
. The magnetic field from the
(2)
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280IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 3, MARCH 2008
Therefore, the BL field coefficient (BFC) of the adjacent MTJ
device can be represented as
(3)
We can use
givenaspecificbasecell.From(3),weseethat
respect to the square of distance. Note that the magnetic field
generatedbytheWWLcurrentcanbeanalyzedinasimilarway,
and represented by the WL field coefficient (WFC)
the BFC of a cell with distance
3000 Å and9000 Å. Then
10% and
scaled down, the distance between adjacent MTJ cells,
reduced, so the influence of magnetic field will be more critical.
Testing failures due to such magnetic field disturbance thus is
important.
Asacomparison,inflashmemoriestherearealsodisturbance
faults induced by high voltages applied to the terminals of the
floating gate transistors.Thedisturbancesaffectcells locatedon
the same row or column of the base cell during programming
or reading. Several disturbance fault models for flash memories
are proposed in [18] and [19]. As described previously, though
the disturbance effect on MRAM decreases with distance, the
victim cell may be disturbed when toggling any cell in certain
neighborhood of the MRAM. Therefore, the disturbance effect
of MRAM is different from that of flash memory. Also, the test
and diagnosis algorithms for flash memories proposed in [18]
and [20] are not suitable for MRAM. In what follows, we intro-
duce the proposed WDF model for MRAM.
to represent the magnetic field of any MTJ device
decreaseswith
. Letbe
from the base cell, and assume
2.7%. When the technology is
, is
B. WDF Model
If the magnetic field on a cell other than the base cell is
large enough such that the MTJ device enters the operating re-
gion, the cell state may change, i.e., disturbance by the base cell
may occur. The thickness and flatness of MTJ devices may af-
fect the characteristics of MRAM [25]. Also, as shown in [26]
and [27], different shapes of the MTJ device may lead to dif-
ferent operation regions. Therefore, due to process variation
and other defects, even the MTJ devices on the same chip may
have different operating regions. Fig. 7 shows the distribution
of MTJ-cell operating regions from the measurement result of
a typical 1-Mb toggle MRAM. In this experiment, we measure
52 MRAM chips. Different colors in Fig. 7 represent different
percentages of good MTJ cells under the corresponding write
currents. For example, there are 90% of the cells that operate
correctly under specific write currents (as marked X in Fig. 7).
We can see that the variation among the cells’ operating regions
is significant. Those MTJ cells with significant shift of their op-
eratingregionmayeasilybedisturbedbythemagneticfieldgen-
erated by the write operation of another MTJ cell, i.e., the data
stored in the bad cell may be inverted (toggled) unexpectedly
during the base cell operation. Because the fault is activated by
the disturbance of the base-cell magnetic field during the write
operation, we call this fault the WDF. The larger the operating
region shift of the victim cell, the more aggressor cells may at-
tack it. For a toggle MRAM, the data stored in the victim cells
Fig. 7. Measured distribution of operating regions of a typical 1-Mb toggle
MRAM.
Fig. 8. Magnetic fields of the cells when writing the base cell.
will be toggled when the fault is activated, instead of exhibiting
stuck-at behavior. Considering the asteroid MRAM, the WDF
may force data stored in the victim cells to 1 or 0, depending on
whether the data written on the aggressor is 1 or 0. The WDF
is suitable for the asteroid MRAM as well. However, we only
focus on the effect of WDF on the toggle MRAM in this paper.
Fig. 8 shows the magnetic fields of other cells when we are
writing the base cell, as specified by the
Again,denotes the magnetic field of an MTJ cell that is
generated by the write currents on another MTJ cell rows and
columns away, and (1,1) represents the magnetic field on the
base MTJ cell during the write operation. Also,
magnetic field of an MTJ cell on the same column but adjacent
row of the base cell; and
cell on the same row but adjacent column of the base cell. For a
fault-free MRAM, by definition, the magnetic field of each base
cell only covers (influences) the node (1,1). It is faulty if there
is a base cell where the field is large enough to cover any other
nodes in Fig. 8. To activate and observe WDF, we can toggle the
data stored in the aggressor cell, then read out the data stored
in the victim cell to verify it. March test algorithms are widely
used for memory testing, which is a class of linear-complexity
andparameters.
is the
is the magnetic field of an MTJ
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SU et al.: WRITE DISTURBANCE MODELING AND TESTING FOR MRAM281
TABLE I
PROPOSED FAULT MODEL AND CORRESPONDING SHORTEST MARCH ELEMENTS
tests with high coverage of conventional RAM faults. We use
the MATS+ test algorithm as an example
The symbols , , and
ascending order, descending order, and either of them, respec-
tively. The
and characters denote the read and write opera-
tions, respectively. The logic values 0 and 1 represent the solid
(all-0 and all-1) data backgrounds [28].
Under a March test, the entire memory cell array is tested se-
rially. Note that if there is even number of write operations in
the aggressor cells, the WDF will be masked, so the number of
write operations in the aggressor cells before reading from the
victim cell should be odd. For ease of test generation, we clas-
sify the WDF into four subsets: 1)
3)
; and 4)
number of aggressors for the given victim cell is even (odd).
For example,
denotes the WDF of a victim where
the number of aggressors with lower address than the victim is
odd, and those with higher address than the victim is even. To
detect the fault, we should approach it from the lowest address,
i.e., theoddside.Therefore,givenan initial stateoftheMRAM,
theMarchelement,
,candetect
shortest March test element for that purpose. The four fault sub-
sets and their corresponding shortest March elements are listed
in Table I. No March element can detect
is no odd side to approach. Also, it is apparent that
can be detected by.
indicate that the address sequence is in
; 2)
denotes that the
;
, where
,anditisthe
, as there
IV. MTJ DEVICE MODELING
Some SPICE models for giant magnetoresistance (GMR) de-
vice are proposed in [29] and [30]. We have also proposed the
SPICE model for asteroid MRAM device in [31]. In this paper,
we modify the behavior of the MTJ device for toggle MRAM.
We now present a SPICE model based on the read/write mech-
anism and physical characteristics of a real toggle MTJ device.
The SPICE model contains three main parts, i.e., the write cir-
cuit, switching and storage circuit, and output circuit. We use a
current controlled voltage source (CCVS) to model the effect of
the magnetic field generated by the programming current on BL
(or WWL). The sub-circuit SPICE models of the toggle cell are
described in the following subsections.
A. Write Circuit
In Fig. 9, we show the write circuit under the programming
currents on BL and WWL, which can invert the present state if
the write sequence of Fig. 4 is performed. Note that
are the magnetic fields generated by
and
and, respectively.
Fig. 9. Write circuit SPICE model.
Fig. 10. Switching and storage circuit SPICE model.
The two dependent voltage sources, EVSR and EVS, are con-
trolled by the voltage over capacitor
stores the present logic state of the cell. After the initial state,
Phaset0,thecapacitor
ischargedtothestateof
t1. Whether
will be charged or discharged in Phase t2 de-
pends on its present charges—
of charge, and vice versa.This means that the present logic state
is pretoggled at the end of Phase t2, however, the state of
remains unchanged.and
bance magnetic fields generated by writing other cells, where
is the total disturbance field generated by other WWLs,
and
is that generated by other BLs. For a cell in the th row,
the corresponding
can be expressed as
(see Fig. 10), which
inPhase
will be discharged if it is full
are used to model the distur-
(4)
where ,
ratio between current and magnetic field, and the magnetic field
generated by the current of the th WWL, respectively. For ex-
ample,
ofa55arrayisthefieldsumof
, and, for
field,
, can be modeled in the same manner by
. With these two dependent sources, the proposed write distur-
bance behavior can be realized.
, and, denote the th WWL in the array, the
,,
. The BL disturbance
instead of
B. Switching and Storage Circuit
The circuit shown in Fig. 10 changes the cell state according
to the stable state of
in the write circuit. The (parallel or
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