Voltage setup problem for embedded systems with multiple voltages
ABSTRACT We formulate the following voltage setup problem: how many levels and at which values should voltages be implemented on the system to achieve the maximum energy saving by dynamic voltage scaling (DVS)? This problem challenges whether DVS technique's full potential in energy saving can be reached on multiple voltage systems. In this paper, 1) we derive analytical solutions for dual-voltage system; 2) we develop efficient numerical methods for the general case where analytical solutions do not exist; 3) we demonstrate how to apply our proposed algorithms in system design; and 4) our experimental results suggest that, interestingly, multiple voltage systems with proper voltage setup can be very close to DVS technique's full potential in energy saving.
Conference Paper: Optimal manufacturing flow to determine minumum operating voltage.[Show abstract] [Hide abstract]
ABSTRACT: A technique to optimize power determines the minimum operating voltage during manufacturing testing on a per die basis. The die is then programmed to operate at the minimum voltage for the life of the die. Silicon results to evaluate the effectiveness of a variety of techniques to determine the minimum voltage of a die, in a manufacturing environment, are presented. Based on this we propose an adaptive hybrid test flow that is guaranteed to compute the minimum voltage while minimizing test time. Finally, sample data on power optimization achievable using power reduction is provided.2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011; 01/2011
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ABSTRACT: In this article, we focus on solving the energy optimization problem for real-time streaming applications on multiprocessor System-on-Chip by combining task-level coarse-grained software pipelining with DVS (Dynamic Voltage Scaling) and DPM (Dynamic Power Management) considering transition overhead, inter-core communication and discrete voltage levels. We propose a two-phase approach to solve the problem. In the first phase, we propose a coarse-grained task parallelization algorithm called RDAG to transform a periodic dependent task graph into a set of independent tasks by exploiting the periodic feature of streaming applications. In the second phase, we propose a scheduling algorithm, GeneS, to optimize energy consumption. GeneS is a genetic algorithm that can search and find the best schedule within the solution space generated by gene evolution. We conduct experiments with a set of benchmarks from E3S and TGFF. The experimental results show that our approach can achieve a 24.4% reduction in energy consumption on average compared with the previous work.ACM Trans. Design Autom. Electr. Syst. 01/2011; 16:14.
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ABSTRACT: In this paper, we combine coarse-grained software pipelining with DVS (Dynamic Voltage/Frequency Scaling) for optimizing energy consumption of stream-based multimedia applications on multi-core embedded systems. By exploiting the potential of multi-core architecture and the characteristic of streaming applications, we propose a two-phase approach to solve the energy minimization problem for periodic dependent tasks on multi-core processors with discrete voltage levels. With our approach, in the first phase, we propose a coarse-grained task-level software pipelining algorithm called RDAG to transform the periodic dependent tasks into a set of independent tasks based on the retiming technique (Leiserson and Saxe, Algorithmica 6:5–35, 1991). In the second phase, we propose two DVS scheduling algorithms for energy minimization. For single-core processors, we propose a pseudo-polynomial algorithm based on dynamic programming that can achieve optimal solution. For multi-core processors, we propose a novel scheduling algorithm called SpringS which works like a spring and can effectively reduce energy consumption by iteratively adjusting task scheduling and voltage selection. We conduct experiments with a set of benchmarks from E3S (Dick 2008) and TGFF (http://ziyang.ece.northwestern.edu/tgff/) based on the power model of the AMD Mobile Athlon4 DVS processor. The experimental results show that our technique can achieve 12.7% energy saving compared with the algorithms in Zhang et al. (2002) on average.Journal of Signal Processing Systems 01/2009; 57:249-262. · 0.55 Impact Factor
Voltage Set-up Problem on Embedded Systems with Multiple Voltages∗
Shaoxiong Hua and Gang Qu
Electrical and Computer Engineering Department and
Institute for Advanced Computer Studies
University of Maryland, College Park, MD 20742, USA
Dynamic voltage scaling (DVS), arguably the most effective energy reduction technique, can be
enabled by having multiple voltages physically implemented on the chip and allowing the operating
system to decide which voltage to use at run-time. Indeed, this is predicted as the future low-power
system by International Technology Roadmap for Semiconductors (ITRS). There still exist many
important unsolved problems on how to reduce the system’s dynamic and/or total power by DVS.
One of such problems, which we refer to as the voltage set-up problem, is how many levels and at
which values should voltages be implemented for the system to achieve the maximum energy saving.
It challenges whether DVS technique’s full potential in energy saving can be reached on multiple-
voltage systems. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For
the general case that does not have analytic solutions, we develop efficient numerical methods that
can take the overhead of voltage switch and leakage into account. (3) We demonstrate how to apply
the proposed algorithms on system design. (4) Interestingly, the experimental results, on both real
life DSP applications and random created applications, suggest that multiple-voltage DVS systems
with only a couple levels of voltages, when set up properly, can be very close to DVS technique’s full
potential in energy saving.
Keywords: System analysis and design, Design automation, Voltage, Energy management.
∗Parts of this manuscript have been published in IEEE/ACM International Conference on Computer Aided Design, pp.
26-29, November 2003.
Energy consumption has become a major design issue for modern embedded systems especially battery-
operated portable devices. The aggressive push for low-power design has prompted the International
Technology Roadmap for Semiconductors (ITRS) to predict that the future system will feature multiple
supply voltages (Vdd), and multiple threshold voltages (Vth), on the same chip . This enables the
dynamic voltage scaling (DVS) technique that varies the supply voltage and clock frequency according
to workload at run time to save energy. DVS achieves the highest energy efficiency for time-varying
computational loads if voltage can be varied arbitrarily [2, 3]. However, physical constraints of CMOS
circuit limit the applicability of having voltage varying continuously and instantaneously. Instead, it
is more practical to make multiple discrete voltages simultaneously available for the system. Many
commercial high-performance microprocessors, such as Transmeta’s Crusoe , AMD’s Athlon 4 ,
Intel’s XScale , and some DSP (digital signal processing) cores developed in Bell Labs all support
voltage scaling for low power.
Most existing work on multiple voltage DVS systems assumes that the voltage set-up, which includes
the number of voltage levels and the voltage value at each level, is given a priori and focuses on developing
the voltage scheduling algorithms to minimize system’s energy consumption [7, 8, 9, 10, 11]. However,
for multiple voltage DVS systems, the energy consumption depends on not only the scheduler but also
the voltage set-up. To the best of our knowledge, how to set up the voltages has been discussed in the
following contexts: Chen and Sarrafzadeh [12, 13] studied the power minimization problem on dual-
voltage system at gate level, where 5.0V was used as the high voltage and different voltages from 2.0V
to 4.2V were used as the low voltage. They suggested that the voltages should be chosen carefully
based on the slack distribution of the circuits. Qu and Potkonjak  gave analytical solutions on how to
build energy efficient communication pipelines under latency constraints by voltage scaling and careful
packet fragmentation, where each pipeline stage receives one fixed voltage. Dhar and Maksimovic 
considered the design of finite impulse response filters and applied Lagrangian method to find the 2N+1
voltages for power minimization, where N is the order of the filter.
In this paper, we consider the following voltage set-up problem at the application level: how to
determine the number of voltages and each voltage value on a multiple-voltage application specific DVS
system such that the system’s energy consumption is minimized? The differences between our work and
the ones mentioned above are: 1) we do voltage scaling at the application level, not the gate level, 2)
we determine the voltage values for any number of voltages, not only for dual-voltage or levels tightly
bounded to the applications, and 3) we also find the best number of voltage levels.
We first use an example to show multiple-voltage system’s energy efficiency and the importance of
the voltage set-up. Suppose that a system periodically executes one application with period equals to 8.
The application’s possible execution times, at the reference voltage 3.3V, are 6, 4, 3, and 2 that occur
with probabilities 0.05, 0.20, 0.45, and 0.30 respectively. The application has a deadline that equals
to its period. Table 1 gives the average energy consumption per iteration when this application is
executed by systems with different voltage set-ups, where the energy is computed based on the optimal
voltage scaling strategies reported in  and  and is normalized to the average energy consumption
per iteration at supply voltage Vdd(ref) = 3.3V and threshold voltage Vth= 0.5V
Table 1: The average energy consumption per iteration on different systems. (1: the reference fixed
voltage system; 2: the best fixed voltage system; 3-6: dual-voltage systems with different voltage set-ups.
1We describe how Table 1 is built.
The average energy consumption per iteration for this application can be expressed as?4
probability that the application requests an execution time (workload) ei and Ei is the minimal energy consumption that
the system completes such workload based on the optimal voltage scaling strategies as we will explain below [3, 7].
First, at the reference voltage Vdd(ref) = 3.3V , the average energy consumption per iteration is EVhigh=3.3V = P(ref)·
iteration. Note that we assume the system shuts down to conserve energy when the current iteration is complete. Otherwise,
the energy consumption becomes 8P(ref) for the always-on system.
Second, the worst case execution time (WCET) 6 is actually less than the deadline 8, we can then utilize this slack to
reduce energy by scaling voltage down. Based on Equation (1) on page 8, one can compute that the lowest voltage to
complete the workload that requires execution time 6 at the reference voltage at time 8 is roughly 2.7V . At this supply
voltage, the average energy consumption per iteration will be 0.67EVhigh=3.3V. Note that system with voltage lower than
2.7V will miss the deadline should the WCET occurs. Therefore, this gives us the minimal energy for fixed-voltage systems.
The rest of Table 1 gives energy consumption of dual-voltage systems. On such system, if the low voltage Vlow provides
sufficient fast speed to complete the application by deadline, the system will operate at Vlowand shut down upon completion.
Otherwise, the system will use Vlowfor some time to complete the workload that requires execution time ti at the reference
voltage before scales up to Vhigh so the computation can be completed on the deadline. ti can be conveniently calculated
i=1pi · Ei, where pi is the
i=1pi · ei = 3.05P(ref), where P(ref) is the power consumption and the sum gives the average execution time per
from the following equation
(ei− ti) +
ti = 8, where ei is the execution time of
the application. This allows us to compute the time that the system is on Vlow and Vhigh and eventually the energy
consumption (see, for example,  and ).
We have two interesting observations from Table 1:
• Multiple-voltage systems in general save more energy over fixed-voltage systems. For example, the
voltage set-ups (Vhigh=3.0V, Vlow=2.0V) and (Vhigh=2.7V, Vlow=1.8V) save more than 35% and
43% energy respectively over the best fixed-voltage system with the lowest voltage 2.7V without
any deadline missing.
• Different voltage set-ups result in significantly different energy reduction as we can see from
the last four columns. Moreover, if not set properly, set-ups 3 (Vhigh=3.3V, Vlow=1.0V) and 4
(Vhigh=3.0V, Vlow=1.0V) for example, the multiple-voltage system may consume more energy
than the best fixed-voltage system, the one with a fixed 2.7V supply voltage in this case.
We formulate and provide practical solutions to the voltage set-up problem that seeks the most
energy efficient voltage setting for the design of multiple-voltage DVS systems. This work is a novel
extension under the DVS research framework. Our main contributions include: (1) analytical solutions
and a linear search algorithm for dual-voltage DVS systems; and (2) an iterative approach and an
approximation method for the general multiple-voltage DVS systems. These results can be used to
guide system design as we show by simulation. Surprisingly, our results show that the 3- or 4-voltage
system can actually be (almost) as energy-efficient as the ideal system that varies voltage arbitrarily.
Finally, we mention that although we restrict most of our discussion to dynamic power reduction (we
do so for the simplicity to explain our approaches and also because that dynamic power still dominates
in embedded system design such as DSP systems), our problem formulation and proposed approaches
can integrate both leakage power/energy model and the overhead on voltage scaling.
The remainder of this paper is organized as follows. In the next section, we survey the related work
on DVS for low power. We then formulate the voltage set-up problem and present the solutions in
Section 3 and Section 4 respectively. Validation of our solutions and experimental results are reported
in Section 5. We conclude the paper in Section 6.
We restrict our survey to the study of multiple-voltage DVS systems. For the discussion on ideal voltage
scaling systems and design/implementation issues on DVS systems, one can find excellent surveys in
[2, 3, 15, 16, 17].
Early research on multiple-voltage DVS systems focused on voltage scheduling at behavioral level,
typically on data flow graphs to exploit the parallelism among all of the operations. Specifically, op-
erations on the critical path are operated at the reference voltage to keep the required throughput,
but operations off the critical path will be executed at reduced voltages to save power and energy
[12, 18, 19, 20, 21]. Raje and Sarrafzadeh  first proposed a multiple voltage scheduling algorithm
to assign voltage level to each operation in a data flow graph to minimize power consumption with a
given computation time constraint. Dual-voltage (5.0V and 3.0V) and three-voltage (5.0V, 3.0V, and
2.4V) were used for experimental purpose. Chang and Pedram  presented a dynamic programming
based algorithm extending this to more general cases (such as cyclic graphs, throughput constraints).
Four voltages (5.0V, 3.3V, 2.4V, and 1.5V) were used in the simulation for no specific reasons. Johnson
and Roy  proposed a datapath scheduling algorithm that iteratively reduces the operating voltage
until no schedule slack remains. Chen and Sarrafzadeh  related the voltage scaling (VS) power
minimization problem on dual-voltage system to the maximal weighted independent set problem, which
is polynomial solvable on transitive graph. They then developed a provably good algorithm to reduce
system’s power consumption. In their simulation, 5.0V was used as the high voltage while different
voltages from 2.0V to 4.2V were used as the low voltage.
The study of multiple-voltage DVS system at high level focused on how to assign voltage to individual
task in order to reduce energy consumption. Ishihara and Yasuura  showed that energy is minimized
only when at most two voltages are applied to a single task. They formulated the voltage scheduling
problem as an integer linear programming problem and relied on solving such problem to obtain the
voltage for each task. Quan and Hu  studied the problem of determining the optimal voltage
schedule for a real-time system with fixed-priority jobs implemented on multiple VS systems. Their
approach was based on an integer programming formulation, which can be efficiently solved. Manzak and
Chakrabarti  proposed periodic and aperiodic task scheduling algorithms for energy minimization
on VS systems. Pillai and Shin  presented a class of algorithms that modify the operating system’s
real-time scheduler and task management service to provide significant energy savings while maintaining
real-time deadline guarantee. Most recently, Hua et al.  have proposed some scheduling strategies
for a multiple-voltage system in order to reduce the system’s energy consumption while providing non-
perfect completion ratio guarantee statistically. Some tasks are intentionally dropped according to their
on-line scheduling algorithm to conserve energy.