Article

An improved model for the slewing behavior of opamps

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 11/1995; DOI: 10.1109/82.471400
Source: IEEE Xplore

ABSTRACT A new time-domain model for the slewing behavior of two-stage
opamps is presented. This model includes the effects of the load
capacitance, compensation capacitance, device sizes and the nonlinear
behavior of the transistors during the slewing period. This model
improves on the commonly used constant current models and allows for
more predictable designs. The model shows good agreement with
simulations. Circuit design results using the traditional and new
improved models are presented

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    • "It can be shown that small-signal-based analyses for the slewing (nonlinear settling) of an opamp [1]–[5] are not suitable for this phase of settling that naturally has nonlinear behavior [6], [7], and large-signal analysis must be used to model the opamp settling behavior in slewing phase. As previously mentioned, a fully differential single-stage folded-cascode structure with short-channel devices is selected as the case study. "
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    ABSTRACT: An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity-saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2009; DOI:10.1109/TCSII.2009.2019169 · 1.19 Impact Factor
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    • "where and is the output voltage change during slewing period. It is worth to mentioning that this architecture has been chosen for its simplicity and the results can be extended to the other two-stage Miller compensated structures without much effort and also for pMOS input pair [1]. Although this model shows good agreement with simulation results, but it can only be used when (3) "
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    ABSTRACT: This brief presents a time-domain model for the slew rate of CMOS two-stage Miller compensated operational transconductance amplifiers. The effects of both the first- and second-stage currents are considered in this model and a simple analytical expression is given in terms of the compensation and load capacitors, output voltage change, and device sizes. HSPICE simulation results are provided to show the validity of the proposed model using a 0.25-μm CMOS technology.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2005; 52(3-52):164 - 167. DOI:10.1109/TCSII.2004.842058 · 1.19 Impact Factor
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    • "− = is a more useful quantity, where T SL is the time it takes the output voltage to change from its original value to the value when the OTA enters the linear region [1]. So, the negative slew rate of NMOS input differential pair two-stage OTAs can be derived as follows: "
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    ABSTRACT: This paper presents a complete time-domain model for the slewing behavior of CMOS two-stage operational transconductance amplifiers (OTAs). In this model, the effects of both first and second stage currents are included. An analytical expression is given in terms of the compensation capacitance, load capacitance and device sizes for each positive and negative slew rates. HSPICE simulation results are provided to show the validity of the proposed models using a 0.35-μm CMOS technology. These models show near perfect agreement with simulation results.
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
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