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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998 259
Propagation Delay and ShortCircuit Power
Dissipation Modeling of the CMOS Inverter
Labros Bisdounis, Student Member, IEEE, Spiridon Nikolaidis, Member, IEEE,
and Odysseas Koufopavlou, Member, IEEE
Abstract— This paper introduces a new, accurate analytical
model for the evaluation of the delay and the shortcircuit power
dissipation of the CMOS inverter. Following a detailed analysis
of the inverter operation, accurate expressions for the output
response to an input ramp are derived. Based on this analysis
improved analytical formulae for the calculation of the propa
gation delay and shortcircuit power dissipation, are produced.
Analytical expressions for all inverter operation regions and
input waveform slopes are derived, which take into account the
influences of the shortcircuit current during switching, and the
gatetodrain coupling capacitance. The effective output transi
tion time of the inverter is determined in order to map the real
output voltage waveform to a ramp waveform for the model to
be applicable in an inverter chain. The final results are in very
good agreement with SPICE simulations.
I. INTRODUCTION
S
devoted for the extraction of accurate, analytical expressions
for timing models of basic circuits. These expressions can be
incorporated in switchlevel and logic simulators, optimizing
the design verification procedure. Much of past research has
addressed the development of delay models for CMOS circuits.
In some of these models [1]–[3] RC circuit approaches were
used in order to map the transistors to equivalent resistors.
However, switchlevel simulators based on RC models tend to
model the average circuit behavior only, since the nonlinear
behavior of the transistors is not well represented by linear
and constant resistors.
Macromodeling approaches in order to achieve efficient de
lay modeling have been proposed. Brocco et al. [4] presented
an approach based on lookup tables which are generated
via precharacterization using SPICE simulations. The methods
which are based on tables with presimulation results are
time consuming and incorporate interpolation errors. Other
approaches derived delay expressions which take into ac
count the slope of the input waveform. However they use
approximations for the load currents by assuming mean charge
conservation across the CMOS structure [5], or use pseu
doempirical factors obtained from SPICE simulations in order
WITCHINGSPEED is one of the most critical perfor
mance parameters in VLSI circuits. Much effort has to be
Manuscript received March 22, 1996; revised January 29, 1997. This paper
was recommended by Associate Editor T. Noll.
L. Bisdounis and O. Koufopavlou are with VLSI Design Laboratory,
Department of Electrical and Computer Engineering, University of Patras,
26500 Patras, Greece.
S. Nikolaidis is with the Electronics and Computers Division, Department
of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece.
Publisher Item Identifier S 10577122(98)01410X.
to evaluate delays in CMOS structures controlled by slowly
varying input signals [6].
Deriving expressions for accurately describing the propaga
tion delay is difficult even though these are for simple gates.
One of the goals of this paper is the analytical evaluation of the
propagation delay in a CMOS inverter. To do this, analytical
expressions of the output waveform are derived, directly from
the differential equation describing the temporal evolution of
the inverter output. It is important to have an accurate model
for the CMOS inverter operation, since several fast methods
for reducing a CMOS gate to an equivalent inverter have
been proposed [7], [8]. By using these socalled “collapsing”
techniques the output response and the propagation delay of
a gate can be computed quickly and accurately without the
complications associated with trying to generalize the inverter
based model to complex gates.
The first closedform delay expression based on the output
response which was obtained directly from the differential
equation describing the CMOS inverter operation was derived
in [9] for a step input. Analytical expressions for the output
waveform and the propagation delay, including the effect of
the input waveform slope, were presented by Hedenstierna
and Jeppson [10]. In this the influences of the shortcircuit
current and the gatetodrain coupling capacitance were ne
glected. These output waveform expressions was extended by
Kayssi et al. [11] for the case of exponential input waveform.
More recently in [12], the differential equation describing
the discharge of the load capacitor was solved for a rising
input ramp considering the current through both transistors
and the coupling capacitance. However, in the case where the
PMOS device is in the linear region, the quadratic term of the
current through the PMOS device was neglected. Moreover,
it was not mentioned how the integration constant between
the linear and the saturation regions of the PMOS device is
calculated for fast inputs. For slow inputs leastsquare fitting
techniques are used. Vemuru and Thorbjornsen [13] derived
an expression for the output waveform, which includes the
previously mentioned quadratic term of the PMOS current but
ignored the influence of the coupling capacitance. A power
series was used to approximate the solution of the differential
equation. However, only the first five terms of the series were
considered, and a recursion form for the calculation of higher
order terms in order to obtain better accuracy was not given.
Sakurai and Newton [14], [15] presented closedform delay
expressions for the CMOS inverter, based on the
power in [15]) law MOS model which includes the carriers’
power ( 
1057–7122/98$10.00 1998 IEEE
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260 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
velocity saturation effect. However, this model requires the
extraction of the empirical velocity saturation index (
) from the static device characteristics for each transistor
width. For the derivation of the output expression in [14],
both the shortcircuit current and the coupling capacitance are
neglected. In [15], in order to approximate the CMOS inverter
by an NMOS circuit, a fictitious input ramp is used which is
clamped to ground for ramp voltages less than the switching
voltage. This approximation is exact only for extreme cases
of input ramps. An extension in the delay expression of [14]
for the case of very lightly loaded inverter and/or slow input
signals is presented in [16]. In this, a table of coefficients
produced from SPICE simulations is used but still neglecting
the shortcircuit current. The delay model presented in [17]
uses the
power MOS model taking into account the short
circuit current of the inverter, but the output voltage and the
currents through both transistors are assumed to be piecewise
linear.
In this paper analytical expressions for the CMOS in
verter output response to an input voltage ramp are derived.
The proposed method overcomes the deficiencies of previous
works. Based on these derived expressions, accurate analytical
formulas for the evaluation of the propagation delay and the
output transition time of the inverter for all the cases of input
ramp slopes are produced. The derived timing model takes into
account the complete expression of the shortcircuit current,
and the input–output coupling capacitance. This is achieved
without using empirical approaches based on simulation results
or approximations for the transistor currents as in previous
works. The simplified bulkcharge MOS model [18] has been
chosen. However, the experience derived from the results
using this model could be expanded to more accurate and
complex models.
The second goal of this paper is the derivation of an analyt
ical expression for the CMOS shortcircuit power dissipation.
This is very important because the growing demand for low
power portable systems has made power dissipation a critical
parameter in chip design [19]. During the output transition in
a static CMOS structure, a direct path from power supply to
ground is created, resulting in a shortcircuit power dissipation.
The first work on the evaluation of the shortcircuit power
dissipation was presented in [20]. A zero load capacitance
and current waveform which is mirror symmetric about a
central vertical axis (at the half of the input transition time)
were assumed. Also, it is considered that the transistor, which
is switched from cutoff to saturation, remains in saturation
during the entire time when shortcircuit current is conducted.
More recently, in [10] and [21] an expression for the short
circuit energy dissipation of the CMOS inverter without the
simplifications of [20] was derived. However, as mentioned
above the expression of the output waveform, was derived
without consideration of the shortcircuit current and the gate
todrain coupling capacitance. A closedform expression for
the evaluation of the shortcircuit power dissipation based
on an expression for the output waveform which considers
the current through both transistors was presented in [22].
Sakurai and Newton [14] presented a formula for the short
circuit energy dissipation during one switching cycle which is
or
a direct extension of the formula presented in [20]. The only
difference is the use of the
power law MOS model instead
of the squarelaw MOS model. Recently, in [23] a substitution
of the input transition time as given in [14] into the formula
for the shortcircuit dissipation also presented in [14], was
proposed. This results in an expression for the shortcircuit
dissipation including the load capacitance which is not agreed
with the initial assumption of zero load capacitance. Vemuru
and Scheinberg [24] proposed a formula for the evaluation of
the shortcircuit power dissipation based on the
model. In this work, the expression of the output waveform
does not include the influences of the shortcircuit current and
the gatetodrain capacitive coupling. A formulation of the
shortcircuit power dissipation through an equivalent short
circuit capacitance is presented in [25], where a rough linear
approximation of the output waveform is used. Recently, in
[26] the shortcircuit current waveform was approximated with
a piecewise linear function of time, in order to estimate the
shortcircuit energy dissipation. However, the energy of the
reverse current due to the gatetodrain coupling capacitance
is subtracted from the shortcircuit energy dissipation resulting
in an underestimation.
In this paper, a formula for the evaluation of the short
circuit power dissipation for the CMOS inverter, based on
analytical expressions of the output waveform is derived. It
takes into account the currents through both transistors without
making simplifying assumptions. In order to achieve better
accuracy and to avoid an overestimation of the shortcircuit
power dissipation, the influence of the gatetodrain coupling
capacitance is considered. The derived expression clearly
shows the influences of the inverter design characteristics, the
load capacitance and the slope of the input waveform driving
the inverter on the shortcircuit power dissipation.
The rest of the paper is organized as follows. In Section II,
analytical expressions of the CMOS inverter output wave
form for all the cases of input voltage ramps, are derived.
Also, in this section a detailed analysis of all the inverter
operation regions is given. Closedform expressions, results
and comparisons with SPICE simulations and previous works
of the propagation delay and the output transition time are
given in Sections III and IV, respectively. Our approach for
the evaluation of the CMOS shortcircuit power dissipation,
results and comparison with previous works are presented in
Section V. Finally, we conclude in Section VI.
power MOS
II. INVERTER OUTPUT WAVEFORM ANALYSIS
The following derivations presented are for a rising input
ramp:
(1)
where
input ramp is similar. Taking into account the gatetodrain
capacitive coupling
, the differential equation which
describes the discharge of the load capacitance
CMOS inverter (Fig. 1), is derived from the application of the
is the input rise time. The analysis for a falling
for the
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BISDOUNIS et al.: PROPAGATION DELAY AND SHORTCIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER261
Fig. 1. The CMOS inverter.
Kirchoff’s current law at the output node
(2)
Consequently, for the rising input ramp of (1), we get
or
(3)
where
The output load consists of the inverter drain junction
capacitances, the gate capacitances of fanout gates and the
interconnect capacitance. The equivalent gatetodrain capaci
tance
is the sum of the gatetodrain capacitances of both
transistors
.

The gatetodrain capacitance of a transistor is the sum of the
gatetodrain overlap capacitance and a part of the gateto
channel capacitance [27]. The overlap capacitance is voltage
independent and is given by

where
the gatetodrain overlap capacitance per unit channel width
which is determined by the process technology. In the cutoff
region of the transistor there is no conducting channel and in
the saturation region the channel does not extend to the drain.
Therefore, the gatetodrain capacitance due to the channel
charge is equal to zero. In the linear region the distributed
gatetochannel capacitance may be viewed as being shared
equally between the source and the drain. Thus, in this case
is the effective width of the transistor and is

where
is the effective length of the transistor.
Depending on the region of operation the NMOS device
current using the simplified bulkcharge MOS model [18] is
is the gate–oxide capacitance per unit area and
given by the following equations:
Cutoff region(4)
Saturation region(5)
Linear region (6)
where
device threshold voltage,
term at the Taylor series expansion of the NMOS bulk
charge equation and
voltage.
The current equations for the PMOS device are
is the NMOS device gain factor,is the NMOS
is the slope of the first order
is the NMOS saturation
Linear region(7)
Saturation region
Cutoff region
(8)
(9)
where
device threshold voltage,
term at the Taylor series expansion of the PMOS bulk–charge
equation and
saturation voltage. The above expressions are similar to those
of the squarelaw MOS model [28] but have the factor
, which reduces the current to a more accurate
value.
In order to give a complete analysis, four cases of input
ramps are considered. First, the case of very fast input ramps
where the PMOS device is turned off after its linear region,
without entering saturation, is studied. Since the input ramp
will reach its final value with the NMOS device either in
saturation or in the linear region, two more cases of input
ramps are considered. For fast input ramps, the NMOS device
is still saturated while for slow input ramps the NMOS is in
its linear region, when the input voltage ramp reaches its final
value. Finally, the case of very slow input ramps where the
PMOS is turned off when the NMOS is in its linear region,
is examined.
In the following, normalized voltages with respect to
i.e.,
is the PMOS device gain factor,is the PMOS
is the slope of the first order
is the PMOS
,
,
and the variable
Case A: The first case to be studied is for very fast input
ramps such that the PMOS transistor is turned off after its
linear region, without entering saturation (Fig. 2). Also, the
NMOS transistor is still saturated when the input voltage
reaches its final value.
, are used.
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262IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
Fig. 2. Operation regions of the inverter for very fast, fast, slow, and very slow input ramps.
Region 1—
PMOS transistor is in the linear region. The first term of the
righthand side of (3) (for
charging current through the coupling capacitance
causes the major influence on the output voltage waveform in
this region. Part of the charge from the input which injected
through this capacitance causes an overshoot at the early part
of the output voltage waveform (Fig. 2). During the overshoot
the PMOS device operates in a reversed linear mode because
the output voltage is greater than the supply voltage. Thus the
PMOS device initially helps to discharge the load capacitance
toward the supply voltage. The differential equation (3) using
(4), (7) becomes a nonlinear Riccati equation [29] which
cannot be solved analytically, if a particular solution is not
known. Thus, a powerseries expansion method [30], [31] has
been used, resulting to the following recursive expression:
: The NMOS transistor is off, and the
) corresponds to the
which
(10)
where
and
for
The second term in the braces for
influence of the quadratic current term of the PMOS device
which was neglected in [12]. A satisfactory limit to truncate
the above series is obtained for
the series is not more than 0.01%.
corresponds to the
. The error of truncating
Region 2—
rated and the PMOS transistor is in the linear region. During
the output voltage overshoot the PMOS device still operates in
a reversed linear mode. As in region 1 the differential equation
(3) using (5), (7) becomes a Riccati equation. In this case,
the powerseries method results to the following recursive
expression:
: The NMOS transistor is satu
(11)
where
for
is the integration constant which is
inserted to ensure continuity with respect to region 1. The
influence of the quadratic current term of the PMOS device
is inserted to the output waveform at the third coefficient of
the series. The truncating error of the above series at
is not more than 0.02%. As shown below, the series output
expressions of regions 1 and 2 give waveforms very close to
those derived from SPICE simulations, which indicates their
validity.
Region 4—
: The NMOS transistor is satu
rated and the PMOS transistor is off. It can be observed in
Fig. 2 that for very fast input ramps (case A), the inverter
doesn’t pass from region 3 because the PMOS device is not
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BISDOUNIS et al.: PROPAGATION DELAY AND SHORTCIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER263
saturated. The analytical solution of the differential equation
(3) in this region is
(12)
The integration constant
with respect to region 2 and is given by
is inserted to ensure continuity
is the value of the output voltage in which the PMOS
device is turned off and is calculated from (11) for
Region 5A—
: The input ramp has reached its
final value with the NMOS device still in saturation and the
PMOS device off.
is the normalized time value where the
NMOS device leaves saturation, i.e.,
current equations). The analytical solution of the differential
equation (3) (for
) is
.
(see NMOS
(13)
Region 6—
ear region and the PMOS is off. The analytical solution of
(3) is
: The NMOS device is entering its lin
(14)
where
(13) for
Case B: The second case studies fast input ramps. The
PMOS transistor is entering the saturation after the linear
region and the NMOS transistor is still saturated when the
input ramp reaches its final value (Fig. 2). The expressions
of the output waveform for regions 1 and 2 are the same
with those of case A. Note, that the right limit of region 2 in
this case is the normalized time value
device is entering the saturation region, i.e.,
(see PMOS current equations). It is determined by the PMOS
saturation condition
, andis calculated from
.
where the PMOS
(15)
Region 3—
The analytical solution of the differential equation (3) is
: Both transistors are saturated.
(16)
The integration constant
with respect to region 2 and is given by
is inserted to ensure continuity
where
the PMOS device is entering the saturation region. For the
is the value of the normalized output voltage when
Fig. 3.
entering region 3.
Approximation of the normalized time ??? when the inverter is
derivation of an analytical output waveform expression and the
calculation of the propagation delay, the integration constant
must be determined. To achieve this, the calculation of
the values
andis required. These values satisfy the
PMOS saturation condition, expressed by (15), and they can
be calculated by solving the system of (11) and (15). Since,
the order of (11) is high, the system of these equations cannot
be solved analytically. Hence, in the following an efficient
method for the calculation of
is illustrated in Fig. 3.
The analytical solution of the differential equation describ
ing the discharge of the load capacitance in region 2, if
negligible PMOS current is assumed, is given by
andis introduced, which
(17)
where
By equating (15) and (17) the normalized time
the inverter is entering region 3 with the assumption of
negligible PMOS current becomes the root of a cubic equation
which belongs to the interval
determination of the tangent of the output waveform expressed
by (11), at the point which corresponds to
tangent is expressed by the equation
in which
. The next step is the
(Fig. 3). This
(18)
where
and
From (15) and (18) an accurate approximation foris
(19)
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264IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
By substituting
is evaluated. The error which is introduced in the calculation of
due to the above method is up to 0.08%. The expressions
of the output waveform for the regions 4, 5A, and 6 are the
same with those of Case A, if the constant
by the constant
.
Case C: In the third case, slow input ramps are studied
(Fig. 2). The NMOS device leaves saturation while the input
voltage is still a ramp. The output expressions for the regions
1, 2, and 3 are the same with those of the previous case.
Region 4—
: The NMOS transistor is sat
urated and the PMOS transistor is off. The solution of the
differential equation which describes the temporal evolution
of the inverter output in this region is given in (12) by
substituting the constant
with
value
is calculated from this equation for
, which corresponds to the NMOS saturation
line (Fig. 2).
Region 5B—
: The NMOS transistor is in the
linear region and the PMOS transistor is off. Neglecting
the charging current through the coupling capacitance an
approximated solution of the differential equation (3) is
in (11) the normalized output voltage
is substituted
. The normalized time
(20)
where
and
Standard ways for the evaluation of the error function can be
found in most mathematical handbooks [32].
Region 6—
: The input ramp has reached its final
value, the NMOS device is still in the linear region and the
PMOS device is off. The differential equation which describes
the operation of the inverter in this region is the same with
those of Case A with different initial conditions. Its analytical
solution is
are the error functions of andrespectively.
(21)
where
normalized output voltage when the input ramp reaches its
final value.
is calculated if
Case D: In this case, very slow input ramps are studied.
The PMOS device is turned off when the NMOS device is
in its linear region. After region 3 the inverter enters directly
to region 5C where the NMOS device is in its linear region
and the PMOS device is saturated. The output waveform
expressions for the regions 1, 2 and 3 are the same with those
of the previous case.
Regions 5C and 5B—
in its linear region for both regions. In region 5B
, the PMOS device is off, while in region 5C
is saturated. The differential equation which describes
andis the value of the
is set in (20).
: The NMOS device is
Fig. 4.
D).
Comparison of PMOS and NMOS device currents in region 5C (Case
the inverter operation, starting from (3), in both regions is
(22)
where
is the Heaviside’s step function (
andforfor.
In region 5C the PMOS device is poorly conducting, thus
its influence can be neglected. In Fig. 4 is shown that for
the PMOS current is up to 0.06% of the
NMOS current. As in Case C (region 5B) the charging current
through the coupling capacitance is neglected and the solution
of the above differential equation is given by (20). In this
case the normalized time value
for
output waveform in region 6 is given by (21).
Typical inverter output waveforms from the above derived
equations, are shown in Fig. 5. The results have been obtained
for an inverter with equal NMOS and PMOS gain factors
mA/V ,
, operating at
of 0.5 pF. In order to give output waveforms for several
values of
the normalized output voltage is plotted as a function of the
normalized time
. The output waveforms produced
from longchannel level 3 SPICE simulations are added for
comparison. It can be observed that the analytical waveforms
are very close to those produced from SPICE simulations. The
output waveforms for
output waveforms for
waveforms for
to Case D.
is calculated from (16),
. The expression for the
and
V with an output load
in the same diagram,
correspond to Case A, the
to Case B, the output
to Case C and those for
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BISDOUNIS et al.: PROPAGATION DELAY AND SHORTCIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER 265
Fig. 5.
method and from SPICE simulations.
Inverter output waveforms derived from the proposed analytical
III. PROPAGATION DELAY
The fall propagation delay at the 50% voltage level is
written as
(23)
where
Thus, for the evaluation of the propagation delay, the normal
ized time value
must be determined for the four cases of
input ramps.
Cases A and B: In the cases of very fast and fast in
put ramps the output voltage reaches the 50% voltage level
when the inverter operates in region 6. The
normalized time value
is calculated from (14) for
is the normalized time value when.
(24)
Case C: In the case of slow input ramps the condition
occurs in region 6 when
5B when
. In the first case the normalized time
value
is calculated from (21) for
or in region
(25)
For the evaluation of
reaches the 50% level in region 5B a linear approximation of
the output voltage is used in the vicinity of the 50% voltage
level, since the expression of the output waveform in region
5B (20) cannot be solved analytically. Then
in the case where the output voltage
(26)
where
output waveform.
is the slope of the
Case D: In the case of very slow input ramps the condition
can occur in three possible regions. For
occurs in region 5B or in region 5C. In this case
the normalized time value
is given by (26). For
occurs in region 3 and
for
is calculated from (16)
(27)
where
is equal to 0 or 4 if
When
a simple quadratic equation.
By substituting
(26), and (27) in (23) the fall propagation delay of the
inverter for all the cases of input ramps can be evaluated
analytically. The error which is introduced in the evaluation
of the propagation delay due to the approximation in the
calculation of
in regions 5B and 5C [see (26)] is up to
0.6%.
In Fig. 6, the fall propagation delay of the inverter is plotted
as a function of
. The results have been produced for an
inverter with equal NMOS and PMOS device gain factors
mA/V ,
, operating atV, with an output load of 0.5
pF, and input rise time from 0.2 ns
. Results using the approaches for the evaluation
of the propagation delay presented in [10], [14] and [17], are
also given. It can be observed, that the presented analytical
method for the evaluation of the inverter propagation delay
gives results closer to those derived from longchannel level
3 SPICE simulations (indicated with diamonds) than the other
methods.
The fall propagation delay as given by (23), for the case
of equal device gain factors and the case of double PMOS
device gain factor, is plotted as a function of
For relatively fast input ramps
shorter for wide PMOS devices than for narrow ones and
higher for slower input ramps. This is due to the charging
current through the gatetodrain coupling capacitance, which
causes a voltage overshoot at the early part of the output
waveform. Initially, the PMOS device helps to discharge
the load capacitance toward supply voltage. Then it causes
or, respectively.
andbecomes the solution of
from one of the equations (24), (25),
and
to 4 ns
in Fig. 7.
the delay is slightly
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266IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
Fig. 6.
previous models and SPICE simulations.
Inverter fall propagation delay derived from the proposed method,
an additional delay in the discharge of the load capacitance
through the NMOS device. For fast input ramps the output
voltage overshoot is high and the first effect dominates the
second, resulting in a reduction of the propagation delay. On
the contrary, for slower input ramps
voltage overshoot is lower and the reaction in the discharge
of the output node caused by the PMOS device current is
dominant. This results in an increase of the propagation delay.
Corresponding results for the rising output propagation delay
are obtained for
as, in this case, the NMOS transistor
is the shortcircuiting transistor.
the output
IV. EFFECTIVE TRANSITION TIME
In real CMOS datapaths, the input signal of a gate is not
a ramp but the output waveform of the preceding gate. In
order for the derived ramp delay model to be applicable to
real circuits, an approximation of the real input waveform by
a ramp waveform is needed, to obtain an effective transition
time. According to [10], a good approximation for the evalua
tion of the effective output transition time
is achieved when the output waveform slope is approximated
by 70% of its derivative at the point which corresponds to the
half supply voltage level (Fig. 8).
for the succeeding inverter in the circuit. The effective output
transition time may then be written as
of the inverter,
can be used as the
(28)
where
waveform at the point
effective output transition time this derivative value must be
determined for all the cases of input ramps.
is the derivative value of the output
. Thus, in order to evaluate the
Fig. 7.
?? ? ???.
Fall propagation delay of the CMOS inverter for ?? ? ?? and
Fig. 8.Determination of the effective output transition time.
Cases A and B: In the cases of very fast and fast input
ramps the derivative value of
using (14)
atis evaluated by
(29)
where
Case C: In the case of slow input ramps the condition
can occur in region 6 or in region 5B. In the
first case
the derivative value of
is evaluated by using (21)
is given by (24).
at
(30)
where
5B
is given by (25). When
, the derivative value of
occurs in region
atis
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BISDOUNIS et al.: PROPAGATION DELAY AND SHORTCIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER267
Fig. 9.
previous models, and SPICE simulations.
Inverter output transition time derived from the proposed method,
calculated by using (20)
(31)
where
and is given by (26).
Case D: In the case of very slow input ramps the condition
can occur in regions 5B, 5C and 3. For
the output voltage reaches the 50% level when the
inverter operates in region 5B or in region 5C. In this case the
derivative value of
at is given by (31). For
occurs in region 3 and the derivative value of
atis evaluated by using (16)
(32)
where
Finally, by substituting the derivative value of
in (28) the effective output transition time of the inverter,
for all the cases of input ramps, is evaluated. The effective
transition time for a falling output waveform is plotted as a
function of
in Fig. 9. The results have been obtained
for an inverter with equal NMOS and PMOS device gain
factors
mA/V ,
, operating at
load of 0.5 pF, and input rise time from 0.2 ns
to 4 ns. Results using the approaches for the
evaluation of the output transition time presented in [14] and
[17], are also given. It can be observed, that the presented
analytical method for the evaluation of the CMOS inverter
output transition time gives results closer to those produced
is given by (27).
at
and
V, with an output
TABLE I
PROPAGATION DELAY RESULTS FOR A CMOS INVERTER CHAIN
from SPICE simulations (indicated with diamonds) than the
other methods. Note, that in the expression presented in [14],
the output transition time remains constant with increasing
values of input transition time. This approach is valid only for
fast input ramps
. This is explained considering that
for fast input ramps the discharging current (current through
the NMOS transistor) takes its maximum value very early
and the PMOS transistor is poorly conducting. As the input
transition time (and consequently
increase of the discharging current is reduced. In addition the
reaction of the PMOS current also increases slowing down
the output transition.
In the following, the propagation delay evaluation for the
CMOS inverter chain of Fig. 10 is examined. The first inverter
(the one outside the box) is only used for the derivation of
a real input waveform to the inverter chain. The inverters
of the chain have different loads and drives. In the delay
evaluation the effective output transition time of each inverter
is calculated by using (28) and is used as input transition time
for the succeeding inverter in the chain. The results derived
from the analytical model and those produced from SPICE
simulations are presented in Table I. The propagation delay of
each inverter and the total delay of the chain are given. The
agreement between the simulation and the calculation is very
good. The error in the total delay is 3.4%.
) increases the rate of the
V. CMOS SHORTCIRCUIT POWER DISSIPATION
In a CMOS inverter, shortcircuit power is dissipated when
a direct path from power supply to ground occurs. For a falling
output transition, due to the charging current through the input
tooutput coupling capacitance
the early part of the output voltage waveform (Fig. 11). During
the overshoot there is no current from power supply to ground
because
is higher than
Fig. 11 (shaded region), shortcircuit power is dissipated from
the end of the output voltage overshoot
PMOS device is turned off
power dissipation is given by
, an overshoot occurs at
. Thus, as it can be seen in
until the
. The shortcircuit
(33)
andare the shortcircuit energy dissipation per
falling and rising output transition, respectively and
switching frequency. In the following, the shortcircuit power
dissipation for all the cases of input ramps is evaluated. The
complete analysis for a falling output transition and final
is the
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268IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 3, MARCH 1998
Fig. 10.Example of a CMOS inverter chain.
Fig. 11.
??? ? ? ? ? ? ??.
Regioninwhichshortcircuitenergyisdissipated
closedform expressions for the shortcircuit energy dissipation
during a rising output transition, are given.
Case A: In this case, the PMOS device is turned off before
the end of the overshoot at the output voltage waveform
(Fig. 2). Thus, there is no shortcircuit power dissipation.
Cases B and C: In both cases of input ramps, the NMOS
device is still saturated when the input voltage ramp reaches
the value
, i.e.,
dissipation during a falling output transition is given by
. The shortcircuit energy
(34)
The application of the Kirchoff’s current law at the inverter
output node (2) gives
(35)
By substituting
in (34) the integration yields
(36)
where
the output voltage overshoot occurs.
normalized output voltage when the PMOS device is turned
off and is calculated from (16) for
is the normalized time value in which the end of
is the value of the
.
The end of the output voltage overshoot occurs in region 2
due to the fact that the discharge of the output node, which is
initially charged at
, does not start in region 1 since the
NMOS device is off. Thus,
. Since this equation cannot be solved analytically, a
method similar with that used for the calculation of
B—region 3) is used. Equation (17) for
normalized time value
in which the end of the overshoot
occurs, if negligible PMOS current is assumed. The tangent
of the output waveform expressed by (11) at the point which
corresponds to
, is given by
must be calculated by (11) for
(Case
gives the
(37)
where
and
By setting
is derived
in (37) an accurate approximation for
(38)
The error which is introduced in the calculation of
the above approximation is up to 0.2%. The analysis in order
to evaluate the shortcircuit energy dissipation during a rising
output transition is symmetrical and results to the following
formula
due to
(39)
is now the input fall time,
in which the end of the output voltage undershoot occurs and
is the value of the normalized output voltage when the
NMOS device is turned off. By substituting
from (36) and (39) in (33), the shortcircuit power dissipation
for the cases of fast and slow input ramps, is evaluated.
is the normalized time value
and
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BISDOUNIS et al.: PROPAGATION DELAY AND SHORTCIRCUIT POWER DISSIPATION MODELING OF THE CMOS INVERTER269
Case D: In this case, the NMOS device is entered in its
linear region, before the input voltage ramp reaches the value
. Thus, the shortcircuit energy dissipation during
the falling output transition is given by
(40)
where
device is entering the saturation region. Using (35) for the
PMOS current in the first integral and the current equation of
the PMOS device in saturation (8) in the second integral, the
shortcircuit energy dissipation is given by
is the normalized time value in which the PMOS
(41)
is the normalized output voltage value in which the PMOS
device is entering the saturation region and
Similarly, the shortcircuit energy dissipation during a rising
output transition is
is given by (38).
(42)
where
value in which the end of the output voltage undershoot occurs
and
is the normalized time value in which the NMOS
device is entering the saturation region.
In Fig. 12, the shortcircuit energy dissipation percentage
of the capacitive energy dissipation in one switching cycle, is
plotted as a function of
. The results have been derived for
an inverter with equal PMOS and NMOS device gain factors
mA/V ,
operating at
Volts, with an output load of 0.5 pF, and
input rise time from 0.2 ns
can be observed in Fig. 12, the percentage of the shortcircuit
energy dissipation increases when the input waveform is slow
compared with the output waveform (high values of
Hence, the contribution of the shortcircuit current to the total
energy increases when the input transition time is increased
and the capacitive load is reduced. SPICE measurements have
been obtained by using the powermeter subcircuit proposed
in [33] and [34]. Also, results using the approaches for the
evaluation of the shortcircuit energy dissipation presented in
[10], [21] and [24] are given. The proposed approach gives
results closer to those derived from SPICE simulations than
the other methods. This occurs because our model includes
the influences of the shortcircuit current and the gateto
drain coupling capacitance on the expression of the inverter
is now the input fall time, is the normalized time
and ,
to 4 ns. As
).
Fig. 12.
dissipation, derived from SPICE simulations and from analytical expressions.
Shortcircuit energy dissipation percentage of the capacitive energy
output waveform. Also, a quite accurate method is used for the
determination of the time where the shortcircuiting transistor
changes from the linear region to the saturation. The models
for the evaluation of the shortcircuit dissipation presented
in [14] and [20] give inaccurate results, because zero load
capacitance is assumed. For example, in an inverter with
identical input and output transition times
shortcircuit energy dissipation in one switching cycle which
is evaluated using (36) and (39) is about 9.5% of the value as
calculated in [14], and 8.5% of the value as calculated in [20].
The validity of the proposed approach has been also examined
for the case of the inverter chain. In the example shown in
Fig. 10 the discrepancy between the analytical calculated value
and that produced from SPICE measurements is about 7.5%.
, the
VI. CONCLUSION
In this paper an accurate analytical method for the eval
uation of the propagation delay and the shortcircuit power
dissipation in a CMOS inverter, has been presented. In order to
achieve that, analytical expressions of the inverter output ramp
response for all the cases of input ramps, have been derived.
These expressions take into account the influences of the short
circuit current and the gatetodrain coupling capacitance.
In addition, the effective transition time of the inverter is
evaluated in order to make the ramp model applicable to real
circuit applications.
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Englewood Cliffs, NJ:
New
Labros Bisdounis (S’95) was born in Agrinio,
Greece, in 1970. He received the Diploma degree
in electrical engineering from the Department of
Electrical and Computer Engineering, University of
Patras, Greece, in 1992. He is currently pursuing the
Ph.D. degree at the VLSI Design Laboratory of the
same department.
His main research interest is on various aspects of
CMOS VLSI design such as circuit timing analysis,
power dissipation modeling, low power and high
speed CMOS digital design.
Spiridon Nikolaidis (S’89–M’93) was born in
Kavala, Greece, in 1965. He received the Diploma
and Ph.D. degrees in electrical engineering from
Patras University, Greece, in 1988 and 1994,
respectively.
Since September 1996 he has been with the
Department of Physics of the Aristotle University
of Thessaloniki, Greece, as a Lecturer in VLSI
design. His research interests include CMOS
gate propagation delay and power consumption
modeling, high speed and low power CMOS circuit
techniques, and high speed and low power DSP architectures.
Odysseas Koufopavlou (S’89–M’90) was born in
Athienou, Cyprus, in 1959. He received the Diploma
of electrical engineering in 1983 and the Ph.D.
degree in electrical engineering in 1990, both from
University of Patras, Greece.
From 1990 to 1994 he was with the IBM Thomas
J. Watson Research Center, Yorktown Heights, NY.
Since 1994, he has been an Assistant Professor at
the Department of Electrical and Computer Engi
neering, University of Patras. His research interests
include VLSI, low power design, and high perfor
mance communication subsystems architecture and implementation. He has
several publications and inventions.
Dr. Koufopavlou is a member of Technical Chamber of Greece.