Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

Dept. of Electr. & Comput. Eng., Patras Univ.
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications 04/1998; 45(3):259 - 270. DOI: 10.1109/81.662699
Source: IEEE Xplore


This paper introduces a new, accurate analytical model for the
evaluation of the delay and the short-circuit power dissipation of the
CMOS inverter. Following a detailed analysis of the inverter operation,
accurate expressions for the output response to an input ramp are
derived. Based on this analysis improved analytical formulae for the
calculation of the propagation delay and short-circuit power
dissipation, are produced. Analytical expressions for all inverter
operation regions and input waveform slopes are derived, which take into
account the influences of the short-circuit current during switching,
and the gate-to-drain coupling capacitance. The effective output
transition time of the inverter is determined in order to map the real
output voltage waveform to a ramp waveform for the model to be
applicable in an inverter chain. The final results are in very good
agreement with SPICE simulations

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    • "In [2], Veendrick developed a closed-form expression for short-circuit power dissipation in an unloaded CMOS inverter. More accurate device models have recently been adopted to analyze short-circuit power [3], [4]. It is shown in [4] that short-circuit power can be as high as 20% of the total active power in high speed, low voltage circuits. "
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    ABSTRACT: Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce significant error when estimating short-circuit power. In order to capture this shielding effect, an effective capacitance of a distributed RLC load is presented for accurately estimating the short-circuit power. The proposed method has been verified with Cadence Spectre simulations. The average error of the short-circuit power obtained with the effective capacitance is less than 7% for the example circuits as compared with an RLC model. This effective capacitance can be used in look-up tables or in empirical -factor expressions to estimate short-circuit power.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 02/2008; 55(1-55):26 - 30. DOI:10.1109/TCSII.2007.907812 · 1.23 Impact Factor
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    • "than an input step. Yet better estimates of propagation delay continue to be published; for example, [8] gives a surprisingly complicated but complete analytical expression for delay, given that the circuit in question contains only an NFET, a PFET, and a capacitor. The complexity of these analyses forces designers to continue to use simple estimates based on RC delay for hand calculation, which are refined on timing simulators [4], [5]. "
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    ABSTRACT: A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for flicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator
    IEEE Journal of Solid-State Circuits 09/2006; 41(8-41):1803 - 1816. DOI:10.1109/JSSC.2006.876206 · 3.01 Impact Factor
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    • "However, the accuracy and efficiency of their formulas largely depend on speculated simple device models and assumptions made for the device operation during signal transitions. For example, [4] [5] [7] [8] [9] all evaluate inverter output waveform under the assumption of zero PMOS device current in order to obtain a solvable closed−form differential equation for output waveform. Then, the output waveform expression is used to deduce actual nonzero PMOS current for time−domain integration which results in total short−circuit power for the signal transition. "
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    ABSTRACT: Power dissipation is becoming a major show stopper for integrated circuit design especially in the server and pervasive computing technologies. Careful consideration of power requirements is expected to bring major changes in the way we design and analyze integrated circuit performance. This paper proposes a practical methodology to evaluate the short-circuit power of static CMOS gates via effective use of timing information from timing analysis. We introduce three methods to estimate short-circuit power of a static CMOS circuit without requiring explicit circuit simulation. Our proposed methodology offers practical advantages over previous approaches, which heavily rely on simple special device models. Proposed approach is experimented with an extensive set of benchmark examples and several device models and found very accurate.
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