SFQ-to-level logic conversion by HTS Josephson drivers for output interface

Fujitsu Ltd., Atsugi, Japan
IEEE Transactions on Applied Superconductivity (Impact Factor: 1.2). 07/2003; DOI: 10.1109/TASC.2003.813867
Source: IEEE Xplore

ABSTRACT Latching-type driver circuits integrated with high-temperature superconductivity (HTS) junctions and two types of resistor were fabricated. These circuits could successfully perform latching operation by means of a single-flux-quantum (SFQ) signal input. Ramp-edge-type HTS junctions were fabricated by interface engineering and showed a hysteretic current-voltage characteristics under a temperature of 50 K. The critical current (Ic) of these 5-micron-wide junctions was about 0.2 mA and the IcRn product was about 1.7 mV at 4.2 K. The circuits included two types of resistors, which were made of RF-magnetron-sputtered indium-tin-oxide (ITO) and Au films. A driver with a parallel 2-junction-stack could convert an SFQ pulse, which was transformed through several Josephson transmission lines (JTL's) from a DC/SFQ circuit, to a 2.3-mV level signal.

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We present a new kind of rapid-single-flux-quantum (RSFQ) output driver together with a pseudomorphic high electron mobility transistor (p-HEMT) amplifier both operating at liquid helium temperature. The passive interconnect including the interchip connection between the RSFQ output driver and the first transistor stage of the semiconductor amplifier is the key element for signal matching and was optimized for minimizing the reflections to the RSFQ circuit. The RSFQ output driver is based on a single-flux-quantum to dc converter and a voltage doubler. The circuit is realized in the Niobium based 1 kA/cm<sup>2</sup> process of FLUXONICS Foundry and provides up to 438-muV output voltage. We demonstrate high-speed experiments of the output driver in combination with two different semiconductor amplifier circuits at liquid helium temperature. The output voltage of a 2-Gb/s data stream was measured to be about 3.5 mV.
    IEEE Transactions on Applied Superconductivity 03/2009; · 1.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J<sub>c</sub> of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J<sub>c</sub> of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO<sub>x</sub>-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J<sub>c</sub> of 45 kA/cm<sup>2</sup>, which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10<sup>-15</sup> for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa<sub>2</sub>Cu<sub>3</sub>O<sub>7-x</sub> have an optimum J<sub>c</sub> of 60 kA/cm<sup>2</sup> that gives the smallest punchthrough probability lower than 10<sup>-15</sup> for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J<sub>c</sub> of 45 kA/cm<sup>2</sup> for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J<sub>c</sub> is important to prepare 40-Gb/s SFQ systems. The J<sub>c</sub> of 60 kA/cm<sup>2</sup> is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.
    IEEE Transactions on Applied Superconductivity 04/2005; · 1.20 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The authors evaluated the operation of high-temperature superconducting quantum interference device (SQUID)-array interface circuits (IFCs) with normal-metal control lines. Transimpedance amplification was obtained at an operating speed of 1 Gb/s using a cryocooler. The effect of the number of SQUIDs connected in series and the number of arrays connected in parallel on the level of output from the SQUID-array IFCs was examined by Josephson circuit simulation, and then the effect of statistical spreads of junction characteristics was evaluated by Monte Carlo simulation. It was found that the configuration of two parallel SQUID arrays with 64 SQUIDs gives the highest output when the junction characteristics in the arrays have a certain spread. The authors fabricated the IFCs by using the conventional interface-engineered junction process. The process reproducibility was 100 μA ±25% for junction I<sub>c</sub>, and 3.02 pH ±5% and 2.57 pH ±17% for the sheet inductance of the upper and lower electrodes, respectively. The transimpedance at low frequencies reached 20 and 4 V/A for input levels of 20 and 100 μA, respectively. Output voltages as high as 4.4 mV at 4.2 K and 2.3 mV at 40 K were obtained. Furthermore, an output voltage of 600 μV was obtained for a 1-Gb/s 2<sup>15</sup>-1 pseudo-random binary signal input at 40 K.
    IEEE Transactions on Applied Superconductivity 04/2004; · 1.20 Impact Factor