Improved critical-current-density uniformity by using anodization
ABSTRACT We discuss an anodization technique for a Nb superconductive-electronics-fabrication process that results in an improvement in critical-current-density Jc uniformity across a 150-mm-diameter wafer. We outline the anodization process and describe the metrology techniques used to determine the NbOx thickness grown. In the work described, we performed critical current Ic measurements on Josephson junctions distributed across a wafer. We then compared the Jc uniformity of pairs of wafers, fabricated together, differing only in the presence or absence of the anodization step. The cross-wafer standard deviation of Jc was typically ∼5% for anodized wafers but >15% for unanodized wafers. This difference in Jc uniformity is suggestive of an in-process modification from an unknown cause that is blocked by the anodic oxide. It is interesting that small junctions do not see an improvement in Ic uniformity - apparently the anodization improves only the Jc uniformity and not the variation in junction size. Control of Jc is important for all applications of superconductive electronics including quantum computation and rapid single-flux quantum (RSFQ) circuitry.
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ABSTRACT: HYPRES has developed new fabrication processes for higher critical current density Josephson junctions (JJs). These processes incorporate an additional anodization step for junction insulation, which enables fabrication of junctions down to submicron sizes. A set of new processing tools has been employed, including a high density (ICP) plasma etching of niobium and aluminum, and low temperature plasma-enhanced chemical vapor deposition of interlayer dielectric (SiO<sub>2</sub>) from a TEOS source. A set of new parametric control monitor (PCM) test chips has been designed and implemented. Results of electric and SEM characterization of JJ's, wiring, and contact-hole etching are presented. The critical current spreads and shunt resistance uniformity along with the effects of junction shape are discussed. The critical current 1σ spreads of 1.2% have been achieved for the 4.5 kA/cm<sup>2</sup> process.IEEE Transactions on Applied Superconductivity 07/2005; · 1.20 Impact Factor
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ABSTRACT: We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines. Comment: 14 pages, 15 figuresSuperconductor Science and Technology 04/2010; 23:065004. · 2.76 Impact Factor
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003 111
Improved Critical-Current-Density Uniformity by
Daniel Nakada, Karl K. Berggren, Earle Macedo, Vladimir Liberman, and Terry P. Orlando
Abstract—We discuss an anodization technique for a Nb
superconductive-electronics-fabrication process that results in an
improvement in critical-current-density
150-mm-diameter wafer. We outline the anodization process and
describe the metrology techniques used to determine the NbO
thickness grown. In the work described, we performed critical
measurements on Josephson junctions distributed
across a wafer. We then compared the
wafers, fabricated together, differing only in the presence or ab-
sence of the anodization step. The cross-wafer standard deviation
was typically5? for anodized wafers but
unanodized wafers. This difference in
of an in-process modification from an unknown cause that is
blocked by the anodic oxide. It is interesting that small junctions
do not see an improvement in
anodization improves only the
in junction size. Control of
is important for all applications of
superconductive electronics including quantum computation and
rapid single-flux quantum (RSFQ) circuitry.
uniformity across a
uniformity of pairs of
uniformity is suggestive
uniformity and not the variation
Index Terms—Anodization, critical-current-density, Josephson
junction fabrication process. Typically, the
150-mm-diameter wafer is
from 0.1–20 kA cm . Highly uniform
quantity of chips per wafer at a given critical-current-density.
Past results suggested that anodization of the junction region
uniformity across a wafer but this suggestion has
never been supported with direct comparisons –. In this
paper, we addressour effortstoincorporate anodization intoour
standard Nb process and we study its effects on
The Josephson junctions were fabricated in a class-10 clean-
room facility at MIT Lincoln Laboratory. We used our standard
ONTROLLING the critical-current-density
across a wafer is a major challenge in the Nb Josephson
variation across a
15for current densities ranging
is desired for pro-
Manuscript received August 6, 2002. This work was supported in part by
the Department of Defense under the Department of the Air Force Contract
F19628-00-C-0002, in part by the Air Force Office of Scientific Research
under Grant F49620-01-1-0457 under the DoD University Research Initiative
on Nanotechnology (DURINT) program, and by ARDA. Opinions, interpreta-
tions, conclusions and recommendations are those of the authors and are not
necessarily endorsed by the Department of Defense.
D. Nakada and T. P. Orlando are with the Department of Electrical Engi-
neering, Massachusetts Institute of Technology, Cambridge, MA 02139 USA
K. K. Berggren, E. Macedo, and V. Liberman are with Lincoln Laboratory,
Lexington, MA 02173-9108 USA (e-mail: email@example.com).
Digital Object Identifier 10.1109/TASC.2003.813658
immediately prior to anodization. Inset shows the AlO
region. b) Junction region after anodization. The surface of the counter- and
base-electrode (B.E.) is converted to a metal-oxide layer approximately 50 nm
thick. The dotted line shows the original surface. Inset shows amount of anodic
oxide grown and consumed. The anodic oxide causes the surface to swell up
and out slightly during growth.
a) Nb Josephson junction after counter-electrode (C.E.) etch but
doubly planarized all-refractory technology for superconduc-
tive electronics process [DPARTS] . The substrates were
150-mm-diameter prime silicon wafers, thermally oxidized
to produce a 500-nm-thick SiO layer. The Nb/Al/AlO /Nb
trilayer was then deposited, followed by patterning of the Nb
counter-electrode (C.E.) using optical projection lithography.
Reactive ion etching (RIE) of the counter-electrode was
performed in a load-locked chamber using SF gas. Because
we felt that after RIE the junction region could be vulnerable
to chemical, plasma and/or other damage from subsequent
processing steps (shown in Fig. 1(a), we anodized the wafer
to form a 50-nm-thick protective metal-oxide layer around the
junction perimeter. Fig. 1(b) shows that after anodization the
junction region is “sealed” from the outside environment by
1051-8223/03$17.00 © 2003 IEEE
112IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003
a thick NbO layer. The remaining steps of the process were
modified slightly to account for the presence of this layer, as
described in Section II.
We first outline the anodization procedure and its incorpo-
ration into the standard Nb superconducting device fabrication
process. We then discuss metrology methods used to determine
the thickness of niobium oxide grown. We follow with a discus-
formity, presenting room-temperature normal-state resistance
measurements of junctions. Finally we conclude with discus-
sion and analysis of our results.
II. ANODIZATION PROCESS DESCRIPTION
The modification of the fabrication process to include an-
odization consisted of three steps: 1) the development of the
anodization process; 2) the integration of the anodization step
into the existing DPARTS process; and 3) the development of
metrology methods for process control. In this section we de-
scribe work in each of these areas.
A. Anodization Process
a current passes through the Nb film in the electrolytic solution,
the surface of the Nb is converted to its oxide form. This oxi-
dation progresses from the solution inward, toward the metal,
with the final thickness determined by the applied voltage. The
metal-oxide layer serves as a protective barrier to further ionic
flow . Anodization processes of this sort have been used ex-
tensively in the past for the fabrication of Nb Josephson junc-
tions , –.
For our process, anodization followed theRIE of thecounter-
electrode and stripping of photoresist, so the anodization was
unmasked. Anodization was performed in an electrolytic solu-
tion of tartaric acid (HOOC CHOH COOH and ammonium
hydroxide (NH OH). 400 g of tartaric acid powder were added
to a recirculating bath of an approximately 5L volume of deion-
ized water. Then a 28–30% NH OH solution was added incre-
mentally until the measured pH was
of NH OH solution added was
process proceeded as follows: (1) A Pt wafer (cathode) in the
electrolytic solution was grounded while the Nb device wafer
of the power supply was ramped, from 0 V to 20 V, maintaining
an initial constant current of 0.225 A through the wafer. The
overall ramp time was approximately 50 sec. (3) The voltage
current through the wafers dropped exponentially as the NbO
layer densified. (4) When the current level reached 10% of its
initial value, the power supply was abruptly switched off. The
total immersion time was approximately 1.5 minutes. After an-
odization, the wafers were cleaned using deionized water in a
dump-rinser and spin-rinser dryer.
(the total volume
300 ml). The anodization
B. Process Integration
Subsequent process steps were modified to account for the
NbO layer. The NbO layer made it difficult to etch through
OPTICAL CONSTANTS OF NB AND NbO . INDEX OF REFRACTION ? AND
ABSORPTION COEFFICIENT ? VALUES VS. WAVELENGTH FOR NB FILM
AND 95 NM THICK NbO FILM
the base-electrode and to gain contact through a via to the base-
and counter-electrode. We modified the RIE etching process for
the base-electrode slightly from that of the other Nb layers by
performing it at a substrate temperature of 80 C (compared to
50 C for the other Nb layers). This elevated temperature was
an etch undercut profile due to the anodic oxide (see Fig. 3(a)).
To achieve contact through the anodic layer at the base of the
via (between the base-electrode/wiring layer and counter-elec-
trode/wiring layer) we relied on the 25% over-etch of the
PECVD deposited oxide and the pre-sputter of the wiring layer
to promote adhesion between the base-electrode and wiring
layer. To achieve contact to the counter-electrode, we used the
polishing from chemical mechanical planarization (CMP) and
the pre-sputter prior to wiring deposition to remove the NbO
grown on the top of the counter-electrode.
C. Thickness Metrology
process control of anodization and for all subsequent dielectric
metrology. In our process, film thicknesses are typically
measured by using spectral reflectometry, for which the optical
constants and thickness of all underlying films are required.
Data available in the literature for bulk and thin-film Nb and
NbO was found to be inadequate: it could not determine the
anodic film thickness accurately from spectral reflectometry
or ellipsometry. We therefore needed to determine the index of
and absorption coefficient
and NbO as a function of wavelength.
To determine the optical constants of NbO we first needed
an independent measure of the film thickness. We used scan-
layer thickness is critical for both
of the underlying Nb
NAKADA et al.: IMPROVED CRITICAL-CURRENT-DENSITY UNIFORMITY BY USING ANODIZATION113
determined both by reflectometry measurements and SEM images. The solid
line represents the best-fit line to the reflectometry data.
NbO film thickness for given anodization voltage. Film thickness is
ning electron microscopy (SEM) images to determine the film
thickness. We then determined the optical properties of the Nb
and NbO film using a Hitachi U-4000 spectrophotometer with
a 12-degree absolute-reflectance attachment. The resulting re-
flectance data was used to extract the index of refraction
as a function of wavelength for a Nb
layer and 95-nm-thick NbO
layer. The results are given in
Table I. NbO data varied by a few percent depending on the
thickness of the oxide; the range of Cauchy coefficients was
small to be important for our purposes therefore we simply used
Cauchy coefficients of
the Cauchy coefficients were
thicknesses extracted from fitting spectral reflectometry data
to measurements from SEM images for a variety of anodiza-
tion voltages and found agreement, as shown in Fig. 2. Finally,
optical reflectometry and SEM data were compared to ellipso-
metric analysis at 632 nm and agreement was also obtained.
As mentioned previously, we used SEM images to estimate
NbO thickness and transmission electron microscopy (TEM)
on a Nb layer is shown in Fig. 3(a). We estimate the thickness
of the NbO layer to be
50 nm for an anodization voltage of
20 V. Sample preparation and TEM imaging of Josephson junc-
tions was performed by MCNC and TEM Analysis Inc. Prior to
(4.2 K) and found to have good quality (
images of the anodized junction region is shown Fig. 3(b).
Comparing anodized/unanodized wafer pairs for wafers with
50 nmof NbO , we determinedfrom step-height measurements
that the thickness of anodized wafers was typically 30 nm
greater than unanodized wafers. From this we conclude that
approximately 20 nm of Nb was consumed in the growth
were zero (the range is too
and). For Nb
. We then compared the film
III. EFFECT OFANODIZATION ONCRITICAL-CURRENT-DENSITY
characteristics of our junctions, we looked at their normal-state
anodized junction showing clearly the sealing of the junction edge by NbO .
Note the clean interface between the counter-electrode and wiring layer where
the NbO has been removed by CMP.
a) SEM image of NbO grown on Nb layer. b) TEM image of an
large quantity of junctions distributed across an entire wafer
using an automatic probing station. From these measurements
we determined critical-current-density uniformity for several
anodized/unanodized wafer pairs where, for each pair, the
trilayers were fabricated together.
at room temperature. We calculated the critical
of a junction from themeasurements for a
A. Room Temperature Measurements
Room temperature measurements using specially designed
test structures were used to determine the overall critical-cur-
rent-density across the wafer. We employed four-point
cross-bridge Kelvin resistor (CBKR) structures to determine
the normal-state resistance
vious studies have shown that the critical current of a junction
can be accurately determined from the room-temperature
measurements . The room-temperature
using an automated probing station (Ruckers and Kolls 683 A
Semi-Automatic Wafer Prober). In order to prevent damaging
our junctions, we took two precautions: First, to prevent
electrostatic discharge (ESD) damage, the probing station pins
were grounded before making contact to the junction pads.
Second, we used the “make before break” method before
applying current through the junction. This method consisted
of introducing a resistive path parallel to the junction such that
the current ran mainly through this resistor. This current path
to the junction was then opened so current then flowed through
the junction. This method prevented voltage from building up
across the junction during the measurement.
of the Josephson junction. Pre-
114IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003
of anodized/unanodized wafer pairs. The wafers shown have ? values ranging
between 10 A?cm and 10 A?cm . Lines connect data points on wafers
whose trilayers were deposited together.
Comparison of cross-wafer critical-current-density standard deviation
termined the approximate value of the critical current
junction. From the known junction area (10
together, the only difference being the presence or absence of
anodization. The percent standard deviation of
5for anodized wafers but
Overall, unanodized wafers had a factor of
deviation compared to anodized wafers. Error in room-temper-
measurements due to the finite lead resistance and
rent-density uniformity .
values obtained at room temperature, we de-
10 m , we then
15for unanodized wafers.
3 higher standard
IV. ANALYSIS AND DISCUSSION
Our results suggest that there exists in-process modification
that is avoided or diminished by anodization. The wafer
pairs we examined were simultaneously subjected to the same
highly uniform oxidation process involved in producing the
tunneling barrier, therefore making it unlikely for one wafer to
differ significantly in
uniformity from the other. Isolating
the cause of the modification remains difficult since many
subsequent processing steps are required to produce useful
junctions. Possible sources of damage or contamination of the
junction barrier include: stress in the Nb film, plasma, and/or
chemical sources(photoresist/developer, phosphoricacid, CMP
slurry). Clearly, anodization reduces cross-wafer
large junctions (
m ) suggesting that the anodic oxide
layer retards attack of the junction. However, from separate
room temperature and low temperature measurements, we
have determined that anodization does not improve cross-wafer
spread of small junctions (
is mainly dominated by sizing variation rather than
and anodization does not appear to affect sizing variation.
m ) since small junction
of an anodization process into an existing Nb superconducting
fabrication process and demonstrating its effect on
mity. We initially developed the anodization procedure, then
determined how to modify the existing standard process to
include the anodization step. This work required thickness
measurements, SEM/TEM imaging and step-height profile
measurements. From the normal-state resistance measurements
of junctions, we then determined the critical-current-density
across anodized/unanodized wafer pairs. Our results show that
anodization allows for higher
wafers than unanodized wafers. This enables us to produce the
1 )cross-chip variation that is required for RSFQ
circuits, and to increase the quantity of chips per wafer with
uniformity across anodized
The authors would like to thank the Lincoln Laboratory
Analog Device Technology Group and X. Meng for helpful
comments and discussion, T. Weir and G. Fitch for help with
room temperature testing, and D. Baker and the Lincoln Labo-
ratory Microelectronics Laboratory for help with fabrication.
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