High resolution ADC system

HYPRES Inc., Elmsfrd, NY
IEEE Transactions on Applied Superconductivity (Impact Factor: 1.32). 07/1997; DOI: 10.1109/77.621783
Source: IEEE Xplore

ABSTRACT We have developed and verified experimentally a novel
high-resolution superconducting ADC architecture based on phase
modulation/demodulation principle and implemented in RSFQ logic. We have
demonstrated an ADC chip providing full implementation of this
architecture, including on-chip decimation filter and multiple-channel
synchronizer. We have also developed a digital ADC evaluation system
consisting of an interface electronics block converting the low-voltage
ADC output to standard TTL form at multi-MHz sampling rate, and a
computerized test station performing data acquisition, processing and
display in real time. Using this system we have demonstrated that for
low-frequency (kHz) signals our ADC chips possess linearity in excess of
16 bits with Spur-Free Dynamic Range over 108 dB, which is an important
benchmark for any high-resolution ADC technology

1 Bookmark
  • [Show abstract] [Hide abstract]
    ABSTRACT: We have designed and tested energy-efficient single flux quantum (eSFQ) circuits for use in practical circuits. The first circuit is a 184-bit shift register for acquisition memory to store short transient events. The second circuit is a 16-bit deserializer integrated with an analog-to-digital converter modulator. The deserializer converts a high speed oversampling delta modulator 1-bit data stream into 16 parallel digital outputs at 1/16 of input data rate. In this work, we report preliminary functional and high-speed operation of some of these eSFQ circuits including their margins of operation at different clock speeds, maximum operation frequencies, and power dissipation.
    Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International; 01/2013
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper is a progress report on the development of a high-resolution analog-to-digital converter (ADC) which uses a phase modulation/demodulation architecture. Presented are an analysis of the performance limitations, proposed design improvements, and recent test results. Test results for new versions of room temperature VXI-based interface and processing modules are also described.
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2 process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.
    IEEE Transactions on Applied Superconductivity 06/2013; 23(3):1301505-1301505. DOI:10.1109/TASC.2013.2240755 · 1.32 Impact Factor