Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions
ABSTRACT Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si0.5Ge0.5 hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.
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ABSTRACT: Front-end dielectric requirements for end-of-the roadmap CMOS and beyond are considered. For the former, we focus on the surface-roughness limited channel mobility and short channel device performance, and on how use of alternative dielectric gate stacks with perhaps larger surface roughness might affect short channel device performance. We find that surface-roughness limited channel mobility can be a misleading predictor of short channel device performance, and, in particular, that perhaps increased surface roughness associated with use of high-k dielectrics may be far less problematic than channel mobility measurements would suggest. Dielectric requirements for two beyond CMOS device concepts, the heterobarrier tunnel FET (HetTFET) and the even more exotic graphene bilayer psuedo-spin FET (BiSFET) are also considered. While these latter devices may or may not ultimately work as hoped, they serve to illustrate how the demands on front-end dielectrics could change radically with emerging technologies, and indeed, how the emergence of beyond CMOS devices could depend critically on advances in dielectric technology.217th ECS Meeting; 01/2010
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ABSTRACT: This paper presents an overview of most recent advances in energy efficient beyond CMOS devices, with particular emphasis on tunneling FETs, ferroelectric FETs and some novel hybrid devices that use combined internal mechanisms for steep switching between off and on states. Their physical mechanisms and practical limits are discussed. Such novel devices categories hold promise for future logic circuit operating at sub-0.5V voltage supply and for reducing by orders of magnitude the subthreshold power consumption. The co-integration of the steep swing switches with high performance CMOS platforms is foreseen as an enabler of novel hybrid circuit and system co-design, featuring both high performance and energy efficient modules.218th ECS Meeting; 01/2010
Conference Paper: Ge/Si Core/Shell Nanowire Structures for Tunneling Devices218th ECS Meeting; 01/2010