Characteristics of Ni/Gd FUSI for NMOS gate electrode applications

Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States
IEEE Electron Device Letters (Impact Factor: 3.02). 08/2007; 28(7):555 - 557. DOI: 10.1109/LED.2007.897889
Source: IEEE Xplore

ABSTRACT This letter investigates the work function tuning of nickel/gadolinium (Ni/Gd) fully silicided (FUSI) gate electrodes on HfSiOx dielectrics. It was found that as the percentage of Gd in the Ni/Gd increased from 10% to 30%, the effective work function value after a one-step 450-degC FUSI anneal decreased from 4.75 to 4.35 eV. In addition, the presence of Gd also resulted in lowering of equivalent oxide thickness (EOT) values. The mechanism for a decreased EOT is attributed to the reduction of low-kappa interfacial layers by the presence of Gd in the gate stack. The decrease in work function is attributed to the creation of oxygen vacancies within the high-kappa layer created by the presence of Gd layer.

  • [Show abstract] [Hide abstract]
    ABSTRACT: A novel method of forming rare-earth (RE)-based interlayers to engineer the work function (Phi <sub>m</sub>) of nickel fully silicided (Ni-FUSI) gates was investigated. An extensive range of RE metals comprising yttrium (Y), erbium (Er), dysprosium (Dy), terbium (Tb), gadolinium (Gd), ytterbium (Yb), or lanthanum (La) were sputtered to form RE-based interlayers (REil's) on SiO<sub>2</sub> dielectric. The interposed REIL enabled Si conduction band-edge (Ec) modulation (~3.8-4.0 eV) of midgap NiSi Phi <sub>m</sub> . Band edge Phi<sub>m</sub> was retained even after a high-temperature annealing was conducted before FUSI. Ni-FUSI gate Phi<sub>m</sub> was tunable to ~4.11-.39 and ~4.25- 4.48 eV by reducing the interlayer thickness and varying the Ni silicide phase, respectively. Improved gate leakage and breakdown voltage were observed for the REiL-incorporated gate stacks. RE-O-Si bonding confirmed that the REIL 's that were formed on SiO<sub>2</sub> were thin RE silicates. The modulation of Ni-FUSI gate Phi<sub>m</sub> was attributed to the presence of interfacial RE-oxygen (RE-O) dipoles and correlated well with the calculated RE-O dipole magnitude. The application of La-based interlayer (LaIL) in a HfO<sub>2</sub> dielectric stack was also investigated, and band-edge NiSi Phi<sub>m</sub> could be engineered by intentionally inserting the La<sub>IL</sub> at the HfO<sub>2</sub>/SiO<sub>2</sub> interface.
    IEEE Transactions on Electron Devices 10/2008; DOI:10.1109/TED.2008.927391 · 2.36 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper investigates the effects of Ho and Er on the sheet resistance and crystallinity of Ni(Ho) and Ni(Er) silicides, the work function (WF) modulation of Ni(Ho) and Ni(Er) fully silicided (FUSI) gate electrodes on SiO2 dielectric, and the FUSI gated SiO2/Si interface trap properties by using high-frequency capacitance–voltage (C–V) and photonic high-frequency C–V measurements. It was found that as the thickness percentage of rare earth (RE) metal in the Ni(Ho) or Ni(Er) increases, the sheet resistance of the silicide increases. The crystallinity decreases in the Ni(Ho) and Ni(Er) silicides, and the crystallinity decreases as the Ho thickness percentage increases. As the thickness percentage of Ho in the Ni(Ho) increases from 13% to 30%, the flatband voltage (VFB) shift increases from −0.19 to −0.27 V. The VFB shifts negatively 0.17 V due to 10% Er incorporation in the Ni(Er). The VFB shift can be attributed to the effective WF decrease which may be due to the crystallinity decrease of Ni(Ho) and Ni(Er) FUSI. The interface trap density Dit calculated from the photonic high-frequency C–V curves is in good agreement with that calculated from the high-frequency and photonic high-frequency C–V curves. The Ho or Er addition does not increase the Dit.
    Microelectronic Engineering 10/2008; 85(10):2032–2036. DOI:10.1016/j.mee.2008.04.025 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper investigates the effects of ion implantation and spike activation anneal on the work function (WF) modulation of Ni fully silicided (FUSI) metal gate on SiO2 dielectrics, and on the FUSI gated SiO2/Si(1 0 0) interface trap properties by using high-frequency capacitance–voltage (C–V) and photonic high-frequency C–V measurements. Undoped Ni FUSI gate has good thermal stability, and its WF before and after forming gas annealing (FGA) is 4.75 eV and 4.74 eV, respectively. As pre-doping and B pre-doping shift the flatband voltage of the Ni FUSI gated MOS capacitor negatively and positively, respectively. As-doped Ni FUSI gate may delaminate or peel off after FGA. Before FGA, a characteristic Dit peak ranging from 5.7 × 1012 to 1.2 × 1013 cm−2 eV−1 was observed at approximately 0.63–0.74 eV above the valence band edge for As-doped and B-doped Ni FUSI gated capacitors which received a spike activation anneal after ion implantation. But such a Dit peak was not observed in undoped Ni FUSI gated capacitors or those doped but without a spike activation anneal. The characteristic peak, which may be related to Pb defects at the SiO2/Si(1 0 0) interface, could be eliminated after FGA.
    Applied Surface Science 12/2008; 255(5):1744–1749. DOI:10.1016/j.apsusc.2008.06.024 · 2.54 Impact Factor
Show more