Impact of NBTI on the temporal performance degradation of digital circuits

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
IEEE Electron Device Letters (Impact Factor: 2.79). 09/2005; DOI: 10.1109/LED.2005.852523
Source: IEEE Xplore

ABSTRACT Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

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    ABSTRACT: Effectively confronting device and circuit parameter variations to maintain or improve the design of high performance and energy efficient systems while satisfying historical standards for reliability and lower costs is increasingly challenging with the scaling of technology. In this paper, we develop methods for robust and resilient six-transistor-cell static random access memory (6T-SRAM) designs that mitigate the effects of device and circuit parameter variations. Our interdisciplinary effort involves: 1) using our own recently developed VAR-TX model [1] to illustrate the impact of interdie (also known as die-to-die, D2D) and intradie (also know as within-die, WID) process and operation variations—namely threshold voltage (Vth), gate length (L), and supply voltage (Vdd)—on future different 16-nm architectures and 2) using modified versions of other well-received models to illustrate the impact of variability due to temperature, negative bias temperature instability, aging, and so forth, on existing and next-generation technology nodes. Our goal in combining modeling techniques is to help minimize all major types of variability and to consequently predict and optimize speed and yield for the next generation 6T-SRAMs.
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    ABSTRACT: As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) became a major threat to reliability of CMOS circuits. This threat may even be more severe in the presence of parameter variations such as temperature and process. This paper presents simulation based analysis of BTI and parameter variations in logic gates. Delay, static and dynamic power consumptions are the metrics considered in the analysis. The simulation results show that while considering BTI only, the impact on delay is strongly temperature and duty cycle dependent. For example, in a NOR gate the delay at 75°C and 50% duty cycle is 56% higher than at 25°C; and at 40% duty cycle is 67% higher than at 60%. The results also show that BTI reduced the static and dynamic power. The analysis is redone for BTI by incorporating parameter variation. Monte Carlo simulation results reveal that BTI impact is exacerbated in the presence of parameter variations with up to 15%.
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    ABSTRACT: The threshold voltage drifts induced by Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) weaken NMOS and PMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin and performance. This paper presents a low area overhead Adaptive Body Bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell’s transistors such that the BTI effect dependency of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, READ SNM degradation by 12.24%, WRITE margin degradation by 2.16%, READ delay by 28.68% and WRITE delay by 32.61% compared to the conventional SRAM cell at 108 seconds aging time.
    IEEE Transactions on Device and Materials Reliability 01/2014; · 1.52 Impact Factor


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