Article

Impact of NBTI on the temporal performance degradation of digital circuits

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
IEEE Electron Device Letters (Impact Factor: 3.02). 09/2005; 26(8):560 - 562. DOI: 10.1109/LED.2005.852523
Source: IEEE Xplore

ABSTRACT Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

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    • "Both models can support different input stress types depending on the solving method: only for DC, AC stress (duty factor dependent) or any kind of input stress including the non-periodic workload. Paul et al. in [24] pioneered the work by performing NBTI analysis through the R-D model in case of the DC voltage stress that resulted in the pessimistic outbound of the BTI degradation. Wang et al. [11] and Kumar et al. [30] applied the signal probability and the activity factor concept to the R-D model, where a non-periodic input stream is converted to its equivalent periodic stream. "
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    • "While the longterm model abstracts circuit operation patterns into aging calculations, the aging-aware library serves as the key bridge between device-level reliability effects and large-scale digital circuit analysis. Previous works use complicated methodologies to predict delay shift due to NBTI [46]–[50]. To reduce the computation cost in such a process, a simple gate delay model is proposed in this section. "
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