Impact of NBTI on the temporal performance degradation of digital circuits

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
IEEE Electron Device Letters (Impact Factor: 3.02). 09/2005; DOI: 10.1109/LED.2005.852523
Source: IEEE Xplore

ABSTRACT Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2014; 22(12):2738-2751. · 1.14 Impact Factor
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    ABSTRACT: Reliability concerns due to Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are increasing in nanometer CMOS memory and digital logic. Conventional chip lifetime enhancement techniques rely on run-time wearout sensors to detect device threshold voltage (Vth) shift. In this work, we present a novel wearout sensing technique using metastability resolution time. The circuit consists of a reference inverter and age-tracking inverter cross-coupled to form a metastable cell. The resolution time of this cell is impacted by temporal Vth shift in the tracking devices. The tracking devices are sized relatively large compared to reference inverter to minimize impact of process induced Vth offset. The resolution time measurement is performed in two stages using a ring oscillator based Time to Digital Converter (TDC). The first stage of measurement establishes a reference precision during run time. In the second stage, the actual resolution time is measured relative to the reference. This alleviates impact of process variation and measurement temperature. Implementation and simulation in 32nm Predictive Technology Model indicate a lightweight sensor with estimated area of ~105μm2 and tracking power of 239nW. The resolution time of the circuit tracks Vth shift due to both NBTI and PBTI. A worst case measurement error at +/-3σ Vth offset is 9.3% of ΔVth. A nominal measurement time of ~1ns provides accurate estimate of Vth shift without allowing recovery time for tracking devices.
    2014 15th International Symposium on Quality Electronic Design (ISQED); 03/2014
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    ABSTRACT: The threshold voltage drifts induced by Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) weaken NMOS and PMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin and performance. This paper presents a low area overhead Adaptive Body Bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell’s transistors such that the BTI effect dependency of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, READ SNM degradation by 12.24%, WRITE margin degradation by 2.16%, READ delay by 28.68% and WRITE delay by 32.61% compared to the conventional SRAM cell at 108 seconds aging time.
    IEEE Transactions on Device and Materials Reliability 12/2014; · 1.54 Impact Factor


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