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560IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 8, AUGUST 2005

Impact of NBTI on the Temporal Performance

Degradation of Digital Circuits

Bipul C. Paul, Member, IEEE, Kunhyuk Kang, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE,

Muhammad A. Alam, Senior Member, IEEE, and Kaushik Roy, Fellow, IEEE

Abstract—Negative bias temperature instability (NBTI) has

become one of the major causes for reliability degradation of

nanoscale circuits. In this letter, we propose a simple analytical

model to predict the delay degradation of a wide class of dig-

ital logic gate based on both worst case and activity dependent

threshold voltage change under NBTI. We show that by knowing

the threshold voltage degradation of a single transistor due to

NBTI, one can predict the performance degradation of a circuit

with a reasonable degree of accuracy. We find that digital circuits

are much less sensitive (approximately 9.2% performance degra-

dation in ten years for 70 nm technology) to NBTI degradation

than previously anticipated.

Index Terms—Negative bias temperature instability (NBTI),

performance degradation, threshold voltage degradation.

I. INTRODUCTION

W

tant issue. Due to an increasing electric field across the thin

oxide, the generation of interface traps under negative bias tem-

peratureinstability(NBTI)inpMOStransistorshasbecomeone

of the most critical reliability issues that determine the lifetime

of CMOS devices [1], [2]. Due to NBTI, the threshold voltage

ofthetransistorincreaseswithtimeresultinginthereduc-

tionindrivecurrent[3],whichinturnresultsintemporalperfor-

mance degradation of circuits. Reliability verification is there-

fore necessary in the early design phase to ensure the function-

ality of circuits for a desired period of time. A good model for

estimating the performance degradation due to NBTI, hence, is

urgently needed. While several efficient models have been pro-

posedtoestimate

degradation[4],[5],onlyafewqualitative

discussionsareavailableintheliteratureonthedrivecurrentand

delay degradation due to NBTI [6]–[8].

Inthisletter,forthefirsttime,weproposeananalyticalmodel

to predict the performance degradation of large digital circuits

basedon

degradationofapMOStransistorduetoNBTI.We

show that the degradation in

delay have the same power-law dependency on time. We also

find that the percentage degradation in circuit performance is

much lower than that of

.

ITH the continuous scaling of transistor dimensions, the

reliability degradation of circuits has become an impor-

and the corresponding circuit

Manuscript received May 10, 2005. The review of this letter was arranged by

Editor E. Sangiorgi.

The authors are with the School of Electrical and Computer Engi-

neering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail:

paulb@ecn.purdue.edu; kang18@ecn.purdue.edu; kufluogl@ecn.purdue.edu;

alam@ecn.purdue.edu; kaushik@ecn.purdue.edu).

Digital Object Identifier 10.1109/LED.2005.852523

We use this model to calculate the performance degradation

of several ISCAS benchmark circuits, which represent a wide

range of digital circuits. Results show that using the proposed

model, the performance degradation of a circuit due to NBTI

can be predicted with a reasonably high degree of accuracy.

II. THEORETICAL ANALYSIS

A. Degradation Model

NBTI is the result of trap generation at Si/SiO interface in

negatively biased pMOS transistors at elevated temperatures.

The interaction of inversion layer holes with hydrogen-passi-

vated Si atoms can break the Si–H bonds, creating an inter-

face trap and one H atom that can diffuse away from the in-

terface (through the oxide) or can anneal an existing trap. The

interface trap generation is modeled successfully in the Reac-

tion–Diffusion framework [4]. In this model, interface trap den-

sity

is expressed as

(1)

where

rates, respectively,

and

is the diffusion coefficient. The bond-breaking rate de-

pends on the accumulation of holes in the inversion layer and

the tunneling of the holes into the oxide to dissociate the Si–

bonds[10].Thus,

dependsontheholedensity ,holecapture

cross-section

, tunneling coefficient

ciation coefficient

, and can be expressed as

where

pend on the electric field

acceleration factor,

, , and

field dependence [10]. Substituting

andare the bond-breaking and hydrogen annealing

is the maximum available Si– density

, and the bond disso-

,

and de-

across the oxide,

are assumed to have weak

, (1) can be simplified to

is the field

(2)

where

the interface traps increase scattering resulting in mobility

degradation. The mobility degradation can be expressed as

an additional

shift [8]. The effective threshold voltage

degradation can be expressed as

represents the field independent terms. Furthermore,

(3)

where m accounts for for excess

dation.

shift due to mobility degra-

0741-3106/$20.00 © 2005 IEEE

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PAUL et al.: IMPACT OF NBTI ON THE TEMPORAL PERFORMANCE DEGRADATION OF DIGITAL CIRCUITS561

Fig. 1.

under NBTI stress. (a) The threshold voltage degradation is calculated using

(3) and the delay degradation is obtained using (7). (vertical dashed line: ten

years) (b) The delays of the inverter and the ring oscillator are obtained through

HSPICE simulation using BPTM 70-nm technology.

Percentage degradation in the threshold voltage and delay with time

B. Gate Delay Degradation Model

The drain current of a transistor in the saturation region can

be approximately represented as

(4)

where

expressed as [7] and [8]

is a constant. The delay of a gate can be approximately

(5)

where

Differentiating (5) with respect to

is the load capacitance andis the supply voltage.

we get

(6)

Substituting

can be rewritten as

from (3) in the form of, (6)

(7)

Fig. 2.

benchmark circuit (1) with worst case ??

activity dependent effect. (b) PDF of ?

simulation was done using BPTM 70-nm technology with ?

(a) Percentage degradation in the performance of ISCAS C432

? ?? NBTI stress and (2) with

degradation based on activities. The

? ? V.

The second term in the right-hand side of (7) is not constant

because

is a function of time. However, due to the loga-

rithmic dependency, this term can be treated as constant for a

specific range of time [e.g., ten years, see Fig. 1(a)]. In this pe-

riod,

will linearly change with

slope

as the degradation. Therefore, by monitoring the

threshold voltage degradation, the change in gate delay can be

easily estimated with a high degree of accuracy.

Fig. 1(b) shows the degradation of threshold voltage and the

corresponding gate (inverter) delay with time. The threshold

voltage degradation was obtained using (3). The inverter delay

was measured through HSPICE simulation using 70-nm BPTM

technology1

V [9]. It can be observed that both the

threshold voltage and the gate delay degradation have the same

slope (0.25) as expected from (7).

It can also be observed from Fig. 1(b) that the degradation

in delay is less than the degradation in threshold voltage. This

can be understood from (6). Since

[within the time range shown in Fig. 1(b)] and

one for short channel transistors, the percentage degradation in

delay will be less than that of the threshold voltage and can be

quantified as

with the same

is greater than

is close to

.

1In SPICE simulation we added an appropriate battery to the pMOS gate to

replicate the effect of ?

change.

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562 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 8, AUGUST 2005

TABLE I

DELAY DEGRADATION OF ISCAS BENCHMARK CIRCUITS UNDER NBTI STRESS

( Single Error Correction, Double Error Detection)

C. Circuit Delay Degradation

The performance degradation of any circuit (considering the

activities of individual transistors) can be estimated as follows.

Thedelayofa circuit

is theaccumulationofallindividual

gate delays

in the critical path, which can be expressed as

, where is the number of gates in the critical

path. Using (7), the performance degradation of a circuit can be

expressed as

(8)

where

based on its switching activity. Note that

lated over a period of time and shows negligible change. Hence,

the slope

of

The performance degradation of a nine-stage ring oscillator,

as expected, shows [Fig. 1(b)] the same slope as

served experimentally [11]). Further, the percentage degrada-

tion is half of that of a single gate because in digital circuits a

low-to-high (l-h) switching is always followed by a high-to-low

(h-l) switching. While a l-h switching is affected due to NBTI,

the h-l switching is not affected.

represents the on-time of a pMOSFET in gate ,

is typically calcu-

versus will not change.2

(also ob-

III. SIMULATION RESULTS

We simulated several ISCAS benchmark circuits to estimate

their performance degradation due to NBTI. We considered

2In this letter, NBTI recovery due to ac operation is not included. However,

this can be included by modifying ? in (1) by a constant factor, which makes

a linear shift in percentage ?

degradation [4] and will not change the time

exponent.

the following two cases: 1)

are the same (worst case condition) and 2)

dividual pMOS transistors are different depending on their

on-time

. The on-time is calculated based on

the switching activity of each individual gate assuming 50%

signal switching probability at primary inputs. Circuit delays

are calculated through static timing analysis [12].

The performance degradation of an ISCAS C432 circuit, as

expected, shows [Fig. 2(a)] the same time exponent as

for both case 1 and 2. Furthermore, despite a wide variation in

[Fig. 2(b)], the performance degradation is almost com-

parable to the worst case degradation [Fig. 2(a)]. Hence, esti-

mating performance degradation with a worst case assumption

will not result in a significant over estimation. Table I shows

the percentage delay degradation of several ISCAS benchmark

circuits with time under both worst case

dependent

NBTI stress. The expected average delay

degradation is about 9.2% (worst case) in ten years, approxi-

mately four times less than

of all pMOS transistors

of all in-

and activity

degradation.3

IV. CONCLUSION

In this letter, we proposed a simple analytical model to es-

timate the temporal delay degradation of digital circuits due to

NBTI.Sincetheperformancedegradationhasthesametimeex-

ponent as

, the conventional burn-in tests will be effective

to predict the degradation due to NBTI and we do not need to

test individual transistors. Hence, this analysis will significantly

help in designing reliable digital circuits.

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3Sequential circuits will also have the similar effect due to NBTI as combi-

national logic and can be similarly predicted.