Article

Impact of NBTI on the temporal performance degradation of digital circuits

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
IEEE Electron Device Letters (Impact Factor: 2.79). 09/2005; DOI: 10.1109/LED.2005.852523
Source: IEEE Xplore

ABSTRACT Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

0 Bookmarks
 · 
85 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2013; 32(6):869-881. · 1.09 Impact Factor
  • Source
    01/2013: pages 155-165;
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.
    IEEE Transactions on Device and Materials Reliability 01/2014; 14(1):182-193. · 1.52 Impact Factor

Full-text

View
2 Downloads
Available from