Impact of NBTI on the temporal performance degradation of digital circuits
ABSTRACT Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.
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ABSTRACT: As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.01/2012;
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ABSTRACT: The importance of mobility degradation (Δμeff) due to Negative Bias Temperature Instability (NBTI) stress is studied for precise modeling of p-MOSFET drain current degradation (ΔID). An improvement to the SPICE mobility model is presented to incorporate Δμeff , and the modified model is validated against experimental ΔID and transconductance degradation (Δgm) over time, in the subthreshold to strong inversion region, across different SiON and high-k metal gate (HKMG) devices. To gain further insight into NBTI mobility degradation, the well-known physics-based mobility model consisting of three scattering components is revalidated across different devices. This analysis is beneficial for device and circuit simulations in Technology CAD and SPICE environments, respectively, for different process technologies.IEEE Transactions on Electron Devices 01/2013; 60(7):2096-2103. · 2.06 Impact Factor
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ABSTRACT: This paper reports a methodology to correlate Hot Carrier Injection (HCI) degradation mechanism and electrical figures of merit on Lateral-Diffused MetalâOxide-Semiconductor (LDMOS) transistor. This method is based on RF life test in radar operating conditions coupled to a high drain voltage in order to make visible HCI degradation. We propose drain current modeling vs. time based on a simple extraction procedure. The electron density trapped in the oxide is extracted from hot carrier induced series resistance enhancement model (HISREM â i.e. ÎRd model). From this methodology, the degradation of RF-LDMOS due to HCI is quantified and could be simulated with EDA.Microelectronics Reliability 01/2011; 51(8):1289-1294. · 1.14 Impact Factor
560IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 8, AUGUST 2005
Impact of NBTI on the Temporal Performance
Degradation of Digital Circuits
Bipul C. Paul, Member, IEEE, Kunhyuk Kang, Student Member, IEEE, Haldun Kufluoglu, Student Member, IEEE,
Muhammad A. Alam, Senior Member, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—Negative bias temperature instability (NBTI) has
become one of the major causes for reliability degradation of
nanoscale circuits. In this letter, we propose a simple analytical
model to predict the delay degradation of a wide class of dig-
ital logic gate based on both worst case and activity dependent
threshold voltage change under NBTI. We show that by knowing
the threshold voltage degradation of a single transistor due to
NBTI, one can predict the performance degradation of a circuit
with a reasonable degree of accuracy. We find that digital circuits
are much less sensitive (approximately 9.2% performance degra-
dation in ten years for 70 nm technology) to NBTI degradation
than previously anticipated.
Index Terms—Negative bias temperature instability (NBTI),
performance degradation, threshold voltage degradation.
tant issue. Due to an increasing electric field across the thin
oxide, the generation of interface traps under negative bias tem-
of the most critical reliability issues that determine the lifetime
of CMOS devices , . Due to NBTI, the threshold voltage
mance degradation of circuits. Reliability verification is there-
fore necessary in the early design phase to ensure the function-
ality of circuits for a desired period of time. A good model for
estimating the performance degradation due to NBTI, hence, is
urgently needed. While several efficient models have been pro-
delay degradation due to NBTI –.
to predict the performance degradation of large digital circuits
show that the degradation in
delay have the same power-law dependency on time. We also
find that the percentage degradation in circuit performance is
much lower than that of
ITH the continuous scaling of transistor dimensions, the
reliability degradation of circuits has become an impor-
and the corresponding circuit
Manuscript received May 10, 2005. The review of this letter was arranged by
Editor E. Sangiorgi.
The authors are with the School of Electrical and Computer Engi-
neering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail:
firstname.lastname@example.org; email@example.com; firstname.lastname@example.org;
Digital Object Identifier 10.1109/LED.2005.852523
We use this model to calculate the performance degradation
of several ISCAS benchmark circuits, which represent a wide
range of digital circuits. Results show that using the proposed
model, the performance degradation of a circuit due to NBTI
can be predicted with a reasonably high degree of accuracy.
II. THEORETICAL ANALYSIS
NBTI is the result of trap generation at Si/SiO interface in
negatively biased pMOS transistors at elevated temperatures.
The interaction of inversion layer holes with hydrogen-passi-
vated Si atoms can break the Si–H bonds, creating an inter-
face trap and one H atom that can diffuse away from the in-
terface (through the oxide) or can anneal an existing trap. The
interface trap generation is modeled successfully in the Reac-
tion–Diffusion framework . In this model, interface trap den-
is expressed as
is the diffusion coefficient. The bond-breaking rate de-
pends on the accumulation of holes in the inversion layer and
the tunneling of the holes into the oxide to dissociate the Si–
, tunneling coefficient
, and can be expressed as
pend on the electric field
, , and
field dependence . Substituting
andare the bond-breaking and hydrogen annealing
is the maximum available Si– density
, and the bond disso-
across the oxide,
are assumed to have weak
, (1) can be simplified to
is the field
the interface traps increase scattering resulting in mobility
degradation. The mobility degradation can be expressed as
shift . The effective threshold voltage
degradation can be expressed as
represents the field independent terms. Furthermore,
where m accounts for for excess
shift due to mobility degra-
0741-3106/$20.00 © 2005 IEEE
PAUL et al.: IMPACT OF NBTI ON THE TEMPORAL PERFORMANCE DEGRADATION OF DIGITAL CIRCUITS561
under NBTI stress. (a) The threshold voltage degradation is calculated using
(3) and the delay degradation is obtained using (7). (vertical dashed line: ten
years) (b) The delays of the inverter and the ring oscillator are obtained through
HSPICE simulation using BPTM 70-nm technology.
Percentage degradation in the threshold voltage and delay with time
B. Gate Delay Degradation Model
The drain current of a transistor in the saturation region can
be approximately represented as
expressed as  and 
is a constant. The delay of a gate can be approximately
Differentiating (5) with respect to
is the load capacitance and is the supply voltage.
can be rewritten as
from (3) in the form of, (6)
benchmark circuit (1) with worst case ??
activity dependent effect. (b) PDF of ?
simulation was done using BPTM 70-nm technology with ?
(a) Percentage degradation in the performance of ISCAS C432
? ?? NBTI stress and (2) with
degradation based on activities. The
? ? V.
The second term in the right-hand side of (7) is not constant
is a function of time. However, due to the loga-
rithmic dependency, this term can be treated as constant for a
specific range of time [e.g., ten years, see Fig. 1(a)]. In this pe-
will linearly change with
as the degradation. Therefore, by monitoring the
threshold voltage degradation, the change in gate delay can be
easily estimated with a high degree of accuracy.
Fig. 1(b) shows the degradation of threshold voltage and the
corresponding gate (inverter) delay with time. The threshold
voltage degradation was obtained using (3). The inverter delay
was measured through HSPICE simulation using 70-nm BPTM
V . It can be observed that both the
threshold voltage and the gate delay degradation have the same
slope (0.25) as expected from (7).
It can also be observed from Fig. 1(b) that the degradation
in delay is less than the degradation in threshold voltage. This
can be understood from (6). Since
[within the time range shown in Fig. 1(b)] and
one for short channel transistors, the percentage degradation in
delay will be less than that of the threshold voltage and can be
with the same
is greater than
is close to
1In SPICE simulation we added an appropriate battery to the pMOS gate to
replicate the effect of ?
562 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 8, AUGUST 2005
DELAY DEGRADATION OF ISCAS BENCHMARK CIRCUITS UNDER NBTI STRESS
( Single Error Correction, Double Error Detection)
C. Circuit Delay Degradation
The performance degradation of any circuit (considering the
activities of individual transistors) can be estimated as follows.
in the critical path, which can be expressed as
, where is the number of gates in the critical
path. Using (7), the performance degradation of a circuit can be
based on its switching activity. Note that
lated over a period of time and shows negligible change. Hence,
The performance degradation of a nine-stage ring oscillator,
as expected, shows [Fig. 1(b)] the same slope as
served experimentally ). Further, the percentage degrada-
tion is half of that of a single gate because in digital circuits a
low-to-high (l-h) switching is always followed by a high-to-low
(h-l) switching. While a l-h switching is affected due to NBTI,
the h-l switching is not affected.
represents the on-time of a pMOSFET in gate ,
is typically calcu-
versuswill not change.2
III. SIMULATION RESULTS
We simulated several ISCAS benchmark circuits to estimate
their performance degradation due to NBTI. We considered
2In this letter, NBTI recovery due to ac operation is not included. However,
this can be included by modifying ? in (1) by a constant factor, which makes
a linear shift in percentage ?
degradation  and will not change the time
the following two cases: 1)
are the same (worst case condition) and 2)
dividual pMOS transistors are different depending on their
. The on-time is calculated based on
the switching activity of each individual gate assuming 50%
signal switching probability at primary inputs. Circuit delays
are calculated through static timing analysis .
The performance degradation of an ISCAS C432 circuit, as
expected, shows [Fig. 2(a)] the same time exponent as
for both case 1 and 2. Furthermore, despite a wide variation in
[Fig. 2(b)], the performance degradation is almost com-
parable to the worst case degradation [Fig. 2(a)]. Hence, esti-
mating performance degradation with a worst case assumption
will not result in a significant over estimation. Table I shows
the percentage delay degradation of several ISCAS benchmark
circuits with time under both worst case
NBTI stress. The expected average delay
degradation is about 9.2% (worst case) in ten years, approxi-
mately four times less than
of all pMOS transistors
of all in-
In this letter, we proposed a simple analytical model to es-
timate the temporal delay degradation of digital circuits due to
, the conventional burn-in tests will be effective
to predict the degradation due to NBTI and we do not need to
test individual transistors. Hence, this analysis will significantly
help in designing reliable digital circuits.
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3Sequential circuits will also have the similar effect due to NBTI as combi-
national logic and can be similarly predicted.