Article

# Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics

Res. Div., IBM Semicond. R&D Center, Yorktown Heights, NY, USA

IEEE Electron Device Letters (Impact Factor: 2.79). 06/2003; DOI: 10.1109/LED.2003.812565 Source: IEEE Xplore

- [Show abstract] [Hide abstract]

**ABSTRACT:**In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). The proposed algorithm is tested for several circuits for 45nm CMOS technology node. The experiments show that average gate leakage reduction are 67.7 % and 80.8 % for SiO<sub>2</sub>- SiON and SiO<sub>2</sub>-Si<sub>3</sub>N<sub>4</sub>, respectively.Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008 - [Show abstract] [Hide abstract]

**ABSTRACT:**We have measured gate current components from the axis perpendicular-to-the-surface. The measured channel magneto-conductance shows also a pronounced magnetic asymmetry, which suggests the channel current is flowing into different crystallographic orientations with different effective masses and hole mobilities. By monitoring the different crystallographic components of the hole flow we have enhanced the understanding of the physics for Si-oxide interface charge transfer and channel conductance in low-dimensional semiconductor devices.01/2012; - [Show abstract] [Hide abstract]

**ABSTRACT:**State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changedInternational Journal of High Speed Electronics and Systems 12/2013; 22(01).

Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.