Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics
ABSTRACT Dependence of CMOS performance on silicon crystal orientation of , , and  has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on  surfaces compared with . CMOS drive current is nearly symmetric on  orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on  substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.
- SourceAvailable from: Shoou-Jinn Chang[show abstract] [hide abstract]
ABSTRACT: In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for comple- mentary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measurements simultaneously. For n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), devices with the increased defect-removal anneal- ing time bring out a significant decrease in the CP current and the 1/f noise. The results indicate that ATR-induced defects are further repaired and consequently achieve a well Si/SiO2 inter- face. In addition, the driving current improvement is observed in devices with a small dimension utilizing the modified ATR process. For p-type MOSFETs (pMOSFETs), the direct-current characteristic, CP, and /f noise results are comparable between both HOT wafers. It means that the modified process would not affect bonded (110) regions and degrade the device performance. Hence, this modified process could be adopted to improve the fabrication of the CMOS on the HOT wafer using the ATR method. Moreover, the physical origins of the /f noise is attributed to a fluctuation in the mobility of free carriers for pMOSFETs and a unified model, incorporating both the carrier- number and correlated mobility fluctuations, for nMOSFETs. Index Terms—Amorphization/templated recrystallization (ATR), charge pumping (CP) measurement, complementary metal-oxide-semiconductor (CMOS), hybrid orientation technol- ogy (HOT), interface property, low-frequency (1/f) noise.IEEE Transactions on Electron Devices 01/2011; 58(6):1635-1642. · 2.06 Impact Factor
- [show abstract] [hide abstract]
ABSTRACT: This paper investigates the impact of surface orientation on V <sub>th</sub> sensitivity to process variations for Si and Ge fin-shaped field-effect transistors (FinFETs) using an analytical solution of the Schrödinger equation. Our theoretical model considers the parabolic potential well due to short-channel effects and, therefore, can be used to assess the quantum-confinement effect in short-channel FinFETs. Our study indicates that, for ultrascaled FinFETs, the importance of channel thickness ( t <sub>ch</sub>) variations increases due to the quantum-confinement effect. The Si-(100) and Ge-(111) surfaces show lower V <sub>th</sub> sensitivity to the t <sub>ch</sub> variation as compared with other orientations. On the contrary, the quantum-confinement effect reduces the V <sub>th</sub> sensitivity to the L <sub>eff</sub> variation, and Si-(111) and Ge-(100) surfaces show lower V <sub>th</sub> sensitivity as compared with other orientations. Our study may provide insights for device design and circuit optimization using advanced FinFET technologies.IEEE Transactions on Electron Devices 01/2011; · 2.06 Impact Factor
Conference Proceeding: Low-Power and Robust SRAM Cells Based on Asymmetric FinFET Structures[show abstract] [hide abstract]
ABSTRACT: In this paper, we investigate the characteristics of low-power and robust SRAM cells based on asymmetric FinFET structures in a 32 nm technology. They are based on asymmetric source and drain structures and include Asymmetric Drain Spacer Extension (ADSE) and Asymmetric Doped Drain (ADD) FinFETs. The study includes two recently introduced 6-T SRAM cells based on these structures. In addition, we propose four transistor driverless (4-TDL) and loadless (4-TLL) SRAM cells based on these asymmetric structures. In the investigation, which compares the structures, the effect of different channel orientations is also considered. The results indicate that for 6-T, 4-TDL, and 4-TLL with different channel orientations asymmetric structures have higher read stabilities than the symmetric ones. In addition, the channel orientation (100) presents a higher read stability for 4-TLL while the channel orientation (110) gives rise to a better read stability for 6-T and 4-TDL. Asymmetric structures, however, have lower read currents where the ADSE structure leads to the least one. In terms of write operation, the asymmetric structures present better stability where 4-T cells outperform the 6-T cell. Finally, the results on static power shows that the ADD FinFET structure provides the lowest static power values due to a better DIBL control.Asia Symposium on Quality Electronic Design; 07/2012
IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 5, MAY 2003339
Performance Dependence of CMOS on
Silicon Substrate Orientation for Ultrathin
Oxynitride and HfO?Gate Dielectrics
Min Yang, Evgeni P. Gusev, Meikei Ieong, Oleg Gluschenkov, Diane C. Boyd, Kevin K. Chan, Paul M. Kozlowski,
Christopher P. D’Emic, Raymond M. Sicina, Paul C. Jamison, and Anthony I. Chou
Abstract—Dependence of CMOS performance on silicon crystal
orientation of (100), (111), and (110) has been investigated with the
equivalent gate dielectric thickness less than 3 nm. Hole mobility
160? has been observed for both oxynitride
and HfO?gate dielectrics on (110) surfaces compared with (100).
CMOS drive current is nearly symmetric on (110) orientation
without any degradation of subthreshold slope. For HfO? gate
dielectrics, an approximately 68% enhancement of pMOSFET
drive current has been demonstrated on (110) substrates at
???? ? ? ??
m, while current reduction in nMOS is around
Index Terms—Charge carrier mobility, inversion layers,
tion for the recent investigations of high-
been shown that gate leakage current can be reduced by orders
of magnitude with high-
gate dielectrics, for example HfO
and Al O , . However, mobility degradation has been ob-
served for high-
gate dielectrics. It has been reported that
hole mobility is much higher in MOSFETs fabricated on (110)
or (111) substrates with conventional SiO –, which may
be an opportunity for devices with high-
be able to minimize the negative effect on the carrier mobility.
While novel structures, for example, finFET  and vertical
MOSFETs ,, enablethedevice channelto befabricated
on various crystal orientations, CMOS fabrication on (110) or
(111) orientation has traditionally been hampered by their in-
ferior gate oxide reliability; although, it was recently reported
that gate oxide quality is actually slightly better on (111) sub-
strate in the direct tunneling regime . With different growth
techniques (chemical vapor deposition versus oxidation), less
pected for some high-
gate dielectrics. As such, CMOS with
N EXPONENTIAL increase in gate leakage current with
decreasing gate oxide thickness is the primary motiva-
materials. It has
gate dielectrics to
Manuscript received January 22, 2003. The review of this letter was arranged
by Editor B. Yu.
M. Yang, E. P. Gusev, K. K. Chan, P. M. Kozlowski, C. P. D’Emic, and
R. M. Sicina are with the IBM Semiconductor Research and Development
Center (SRDC), Research Division, T. J. Watson Research Center, Yorktown
Heights, NY 10598 USA.
M. Ieong, O. Gluschenkov, D. C. Boyd, P. C. Jamison, and A. I. Chou are
with the IBM Semiconductor Research and Development Center (SRDC), Mi-
croelectronics Division, Hopewell Junction, NY 12533 USA.
Digital Object Identifier 10.1109/LED.2003.812565
orientations are promising candidates for future low-power and
high-performance applications. In the present work, we demon-
strate for the first time carrier mobility and device performance
of CMOS on (100)-, (110)-, and (111)-orientated silicon sub-
gate dielectrics fabricated on various silicon substrate
cated on 8-in p-type silicon substrates in (100), (111), and (110)
crystal orientations, based on standard processes with modifi-
cations for high-
gate dielectrics . Control devices with
conventional oxynitride were processed simultaneously. After
shallow trench isolation, well implantation, and annealing, a
HfO gate dielectric layer was deposited by atomic layer chem-
ical vapor deposition (ALD) with a thin (
oxynitride , . Ultrathin oxynitride was grown on the con-
trol devices in a conventional furnace at 800 C in N O at-
mosphere. Polycrystalline silicon gate was then deposited and
patterned followed by spacer formation, source–drain implan-
tation, and activation annealing at 1000 C. Cobalt silicidation
was employed to reduce contact resistance and tungsten plugs
used to connect to the copper metal layer.
III. MEASUREMENT RESULTS
The film thickness of HfO gate dielectrics and its varia-
tion across an entire wafer are found to be crystal orientation
independent. The mean thickness (
capacitor biased at accumulation, after correction for quantum
effect , , is about 1.6 nm. In contrast, the
tride grown on (110) substrates is noticeably larger than those
on (111) or (100) substrates, with larger thickness variation on
(110). The gate leakage currents of these gate dielectrics, taken
plottedinFig.1. ForHfO ,gate leakagecurrentis crystal orien-
tation independent and is significantly (more than three orders
of magnitude) lower than that of oxynitride for the same equiv-
alent thickness. In the present work, we observed that the gate
leakage currents of oxynitride grown on (111) and (110) silicon
substrates are similar to those grown on (100) substrates for the
same equivalent thickness with
The inversion layer mobility in large area CMOS (Fig. 2)
was extracted from the drain conductance
) extracted from a large
in the range of 2–3 nm.
in the linear re-
0741-3106/03$17.00 © 2003 IEEE
340 IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 5, MAY 2003
gate dielectrics on (100)-, (111)-, and (110)-orientated silicon substrates at
1 V above flat band voltage as a function of equivalent oxide thickness (?
measured from capacitor at accumulation.
Gate leakage current of HfO (solid dots) and oxynitride (open dots)
gion and the inversion charge
channel inversion capacitance. Hole mobility of devices with
HfO is dramatically larger on (110) substrates than on (100),
with about 162% and 78% increases at an inversion charge den-
sity of 7
10cmfor current flow along
directions, respectively, while the enhancement is about 63%
on a (111) surface with current flow along
hole mobility enhancement in (110) and (111) orientations is
consistent with what has been reported for gate oxide over the
wide range from
100 nm down to 1.5 nm – and was
explained by the anisotropy of the effective mass. In contrast
to the holes, electron mobility is highest for the devices fabri-
cated on the (100) substrates. At an inversion charge density of
10cm, the electron mobility of nMOS with HfO on a
by 49% and 34% with current flows along
rections respectively, while the degradation is 27% on a (111)
surface with current flow along
directions affect both hole and electron mobility dramatically
on (110) substrate but relatively little on (111) substrate.
It has been widely reported for CMOS fabricated on (100)
substrates that carrier mobility is lower in CMOS with high-
dielectrics compared with conventional oxide or oxynitride,
possibly due to fixed charge, charge trapping, and remote
phonon scattering . It is observed in this work that hole
mobility of HfO
is consistently lower than that of oxyni-
tride on (100), (110), and (111) substrates, with degradation
about 5%–10%. For electrons, mobility degradation of HfO
devices mainly occurs at low inversion charge density (low
vertical field), where mobility is limited by column scat-
tering. Thus, fixed or trapped charges in the high-
have significant impact. At high inversion charge densities
810 cm), where mobility is limited by surface
roughness scattering, electron mobility on (110) surfaces is
the about same for devices with HfO
dielectrics. Note that due to charge trapping, the uncertainty in
inversion charge density may shift the mobility curves of HfO
along theandaxes in Fig. 2.
Fig. 3 shows CMOS device performance on various sub-
m for HfO gate dielectrics. For
simplicity, only channel current flow along
determined by the gate to
direction. Current flow
and oxynitride gate
(100)-, (111)-, and (110)-orientated silicon substrates for HfO
oxynitride (dots) gate dielectrics. Nominal current flow on (100), (111), and
(110) surfaces are in ?????, ????? and ????? directions, respectively (solid
lines and open dots). Carrier mobility on (111) and (110) surfaces are also
shown for current flow in the perpendicular directions, i.e., ????? and ?????,
respectively (dashed line and solid dots).
(a) Hole and (b) electron mobility in CMOS devices fabricated on
directions are shown for (110) and (111) substrates, respec-
tively. Interface charge density is known to be higher for oxide
grown on (111) and (110) surfaces; however, its impact on
the subthreshold slope will be less as gate oxide thickness
is decreasing. It has been found in the present work that the
subthreshold slope is not affected by crystal orientation for
both oxynitride and HfO gate stacks, where oxide (or oxide
interfacial layer underneath HfO ) on the silicon is ultrathin.
The threshold voltage of devices on (110) and (111) substrates
are shifted from that on (100) because of different fixed charge
voltage shift should also be considered because of different
effective masses in silicon of (111) and (110) orientations. The
threshold voltages of all the HfO devices are shifted from their
oxynitride counterpart mainly due to the fixed charges. The
output characteristics of these devices are also shown in Fig. 3
for HfO . Drain current at a gate overdrive of 0.9 V and drain
voltage of 1.2 V is increased by 68% and 36% for pMOSFETs
on (110) and (111) substrates, respectively, compared with
those on (100) substrate, while it is decreased by 26% and 5%
for nMOSFETs. It is noticeable that orientation dependence
YANG et al.: PERFORMANCE DEPENDENCE OF CMOS ON SILICON SUBSTRATE ORIENTATION 341
fabricated on silicon substrates with (100) (dashed lines), (110) (solid lines),
and (111) (circles) crystal orientations, with current flow along ?????,
?????, and ?????, respectively. Channel length ?
gate dielectric is HfO with ?
(oxide thickness extracted from inversion
capacitance) of 2.8 and 3.0 nm for nMOS and pMOS, respectively. Note that
the thickness of high-? gate dielectrics is orientation independent.
(a) Subthreshold and (b) output performance of CMOS devices
is 0.12 ?m and the
of drive current is reduced when the channel length is scaled
down to the submicron regime due to velocity saturation. The
same trend is also seen on the devices with oxynitride gate
Conventional CMOS on (100) substrates provides about
twice as much drive current in n-channel MOSFETs than in
p-channel due to the lower hole mobility, pushing pMOSFET
to a larger channel width in logic circuit designs. Unlike
strained-silicon CMOS with mostly electron mobility enhance-
ment , resulting in pMOS performance lagging further
behind nMOS, the drive current of nMOS and pMOS on (110)
substrates are almost equal when current flow is along the
direction. However, gate oxide grown on (110) surfaces
has a larger thickness variation and increased roughness at the
Si–SiO interface. This detrimental orientation dependence of
gate dielectric reliability might be reduced for high-
materials, opening the opportunity for CMOS to be fabricated
on silicon substrates of various orientations. To maximize the
advantage of crystal orientation dependence on carrier mobility,
nMOS should be fabricated on (100) surfaces while pMOS on
Electron and hole mobility has been measured in CMOS
devices fabricated on silicon substrates with various crystal
orientations. Significant hole mobility enhancement has been
observed for devices made on (110) orientation than (100)
orientation, with an increase of
and HfO . Traditionally, the performance of pMOSFETs lags
behind nMOSFETs; however, the increased drive current in
p-channel MOSFETs on (110) crystal orientation provides an
opportunity to reduce the gap in logic applications. Implemen-
tation of HfO gate material with CMOS on (110) or (111)
orientated silicon substrates or surfaces may not be affected by
the orientation dependence of gate dielectric quality, which on
the other hand can be an issue for conventional oxynitride.
160for both oxynitride
The authors would like to thank J. Cai and M. Fischetti of
IBM for their helpful discussions.
 D. A. Buchanan, E. P. Gusev, and E. Cartier et al., “80 nm poly-silicon
gated n-FET’s with ultra-thin Al O gate dielectric for ULSI applica-
tions,” in IEDM Tech. Dig., 2000, pp. 223–226.
 E. P. Gusev, D. A. Buchanan, and E. Cartier et al., “Ultrathin high-?
gate stacks for advanced CMOS devices,” in IEDM Tech. Dig., 2001,
 T. Sato, Y. Takeishi, and H. Hara, “Mobility anisotropy of electrons in
inversion layers on oxidized silicon surfaces,” Phys. Rev. B, vol. 4, pp.
, “Effects of crystallographic orientation on mobility, surface state
density, and noise in p-type inversion layers on oxidized silicon sur-
faces,” Jpn. J. Appl. Phys., vol. 8, pp. 588–598, 1969.
 S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of
inversion layer mobility in Si MOSFET’s: Part II-Effects of surface ori-
entation,” IEEE Trans. Electron Devices, vol. 41, pp. 2357–2362, Dec.
 M. Kinugawa, M. Kakumu, T. Usami, and J. Matsunaga, “Effects of
Dig., 1985, pp. 581–584.
 H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi,
and H. Iwai, “Ultrathin gate oxide CMOS on (111) surface-orientated Si
 H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshima,
“110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFET’s on
(110) surface-oriented Si substrate,” in Symp. VLSI Tech. Dig., 2002,
 J. Kedzierski, D. Fried, and E. Nowak et al., “High-performance
symmetric-gate and CMOS-compatible ?
devices,” in IEDM Tech. Dig., 2001, pp. 437–440.
 R. Weis, K. Hummler, and H. Akatsu, “A highly cost efficient ??
DRAM cell with a double gate vertical transistor device for 100 nm and
beyond,” in IEDM Tech. Dig., 2001, pp. 415–418.
 J. M. Hergenrother, G. D. Wilk, and T. Nigam et al., “50 nm vertical
replacement-gate (VRG) nMOSFET’s with ALD HfO and Al O gate
dielectrics,” in IEDM Tech. Dig., 2001, pp. 51–54.
nMOSFET’s,” IEEE Electron Device Lett., vol. 18, pp. 209–211, 1997.
 S.-H. Lo, D. A. Buchanan, Y. Taur, L. -K. Han, and E. Wu, “Modeling
and characterization of ?
in Symp. VLSI Tech. Dig., 1997, pp. 149–150.
 K. Rim, J. Chu,andH. Chen et al.,“Characteristics and devicedesign of
sub-100 nm strained Si N and PMOSFET’s,” in Symp. VLSI Tech. Dig.,
2002, pp. 98–99.
polysilicon-gated ultra thin oxides,”