Article

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics

Res. Div., IBM Semicond. R&D Center, Yorktown Heights, NY, USA
IEEE Electron Device Letters (Impact Factor: 3.02). 06/2003; 24(5):339 - 341. DOI: 10.1109/LED.2003.812565
Source: IEEE Xplore

ABSTRACT Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.

Download full-text

Full-text

Available from: Christopher D'Emic, Jun 03, 2015
0 Followers
 · 
141 Views
  • Source
    • "In the device simulations, the drift-diffusion model along with high field saturation was used for transport. The carrier mobilities were also calibrated using the experimental data for FinFETs [14]. The results are in good match with the results presented in [7][8]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we investigate the characteristics of low-power and robust SRAM cells based on asymmetric FinFET structures in a 32 nm technology. They are based on asymmetric source and drain structures and include Asymmetric Drain Spacer Extension (ADSE) and Asymmetric Doped Drain (ADD) FinFETs. The study includes two recently introduced 6-T SRAM cells based on these structures. In addition, we propose four transistor driverless (4-TDL) and loadless (4-TLL) SRAM cells based on these asymmetric structures. In the investigation, which compares the structures, the effect of different channel orientations is also considered. The results indicate that for 6-T, 4-TDL, and 4-TLL with different channel orientations asymmetric structures have higher read stabilities than the symmetric ones. In addition, the channel orientation (100) presents a higher read stability for 4-TLL while the channel orientation (110) gives rise to a better read stability for 6-T and 4-TDL. Asymmetric structures, however, have lower read currents where the ADSE structure leads to the least one. In terms of write operation, the asymmetric structures present better stability where 4-T cells outperform the 6-T cell. Finally, the results on static power shows that the ADD FinFET structure provides the lowest static power values due to a better DIBL control.
    Asia Symposium on Quality Electronic Design; 07/2012
  • Source
    • "The HOT provides promising opportunities for the fabrication of MOSFET devices due to the significant performance boost provided by the use of (100)-orientated Si (the orientation in which the electron mobility is higher) and (110)-orientated Si (the orientation in which the hole mobility is higher) for n-and pMOSFETs, respectively [1], and a current 0018-9383/$26.00 © 2011 IEEE Fig. 2. Schematic cross-sectional and X-TEM pictures of CMOS devices fabricated on the HOT wafer. flow in the 110 direction provides the highest drive currents for both types of devices [2]–[4]. Various implementations of this technology have been demonstrated by using silicon-on-insulator (SOI) substrates with either one [5] or both [6] types of devices on an insulating layer, but these solutions proposed for the implementation of the HOT on the SOI substrate require selective epitaxial growth, which involves significant process complexity and cost. "
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, for the hybrid orientation technology (HOT), we propose a modified amorphization/templated recrystallization (ATR) process to improve the material quality. The characterization of Si/SiO2 interface properties for comple- mentary metal-oxide-semiconductor (CMOS) devices fabricated on HOT wafers is demonstrated through charge pumping (CP) and low-frequency (1/f) noise measurements simultaneously. For n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), devices with the increased defect-removal anneal- ing time bring out a significant decrease in the CP current and the 1/f noise. The results indicate that ATR-induced defects are further repaired and consequently achieve a well Si/SiO2 inter- face. In addition, the driving current improvement is observed in devices with a small dimension utilizing the modified ATR process. For p-type MOSFETs (pMOSFETs), the direct-current characteristic, CP, and /f noise results are comparable between both HOT wafers. It means that the modified process would not affect bonded (110) regions and degrade the device performance. Hence, this modified process could be adopted to improve the fabrication of the CMOS on the HOT wafer using the ATR method. Moreover, the physical origins of the /f noise is attributed to a fluctuation in the mobility of free carriers for pMOSFETs and a unified model, incorporating both the carrier- number and correlated mobility fluctuations, for nMOSFETs. Index Terms—Amorphization/templated recrystallization (ATR), charge pumping (CP) measurement, complementary metal-oxide-semiconductor (CMOS), hybrid orientation technol- ogy (HOT), interface property, low-frequency (1/f) noise.
    IEEE Transactions on Electron Devices 01/2011; 58(6):1635-1642. DOI:10.1109/TED.2011.2126047 · 2.36 Impact Factor
  • Source
    • "The reasons for better intrinsic performance of FinFETs can be traced to the reduction of the vertical electric field in the fully-depleted channel, as well as to the difference in electron mobility in (111)/<112> surface channels as compared to the (110)/<112> orientation. Data on electron transport on the (111)/<112> surface show higher mobility than on (110)/<110> and (110)/<100> surfaces [16] [17], and the measured advantage of the FinFETs' intrinsic performance over wide tri-gate devices suggests that the cause can be linked to the higher 9/22 electron mobility on the (111)/<112> surface over that of (110)/<112>. This reduces the contribution of the top gate in the wide tri-gates, but a more accurate evaluation of these effects would require a smaller spread in the measured data. "
    [Show abstract] [Hide abstract]
    ABSTRACT: FinFETs with ultra-large height-to-width ratio have been processed on (1 1 0) bulk silicon wafers by employing crystallographic etching of silicon with TMAH, which results in nearly vertical sidewalls with a (1 1 1)/〈1 1 2〉 surface orientation. Tall fins, which corresponds to wide transistor channels per single fin offer more efficient use of the silicon area and improved performance for multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins demonstrate the downscaling potential of the technology and devices with a height of the active part of the fin of 625 nm have the largest aspect-ratio of the fins reported thus far. Both devices with highly and moderately scaled fin-widths exhibit excellent subthreshold performance while electrons have higher mobility in 15-nm-wide FinFETs, which gives them larger on-state currents. The comparison between FinFETs and wide tri-gate devices shows that FinFETs have better current drivability in this simple process, even with larger source/drain series resistances. The differences in threshold voltage and low-field electron mobility between 1.9-nm-wide and 15-nm-wide FinFETs have been related to the increase in subband energies due to carrier confinement in the extremely narrow fins.
    Solid-State Electronics 05/2010; 54(9):870-876. DOI:10.1016/j.sse.2010.04.021 · 1.51 Impact Factor
Show more