Impacts of gate structure on dynamic threshold SOI nMOSFETs
ABSTRACT The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.
IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 8, AUGUST 2002497
Impacts of Gate Structure on Dynamic Threshold
Wen-Cheng Lo, Sun-Jay Chang, Chun-Yen Chang, Fellow, IEEE, and Tien-Sheng Chao, Senior Member
Abstract—The effects of different substrate-contact structures
(T-gate and H-gate) dynamic threshold voltage silicon-on-insu-
lator (SOI) nMOSFETs (DTMOS) have been investigated. It is
found that H-gate structure devices have higher driving current
than T-gate under DTMOS-mode operation. This is because
H-gate SOI devices have larger body effect factor ? ?, inducing
a lager reduction of threshold voltage. Besides, it is found that
drain-induced-barrier-lowering (DIBL) is dramatically reduced
for both T-gate and H-gate structure devices when devices are
operated under DTMOS-mode.
Index Terms—Dynamic threshold MOS (DTMOS), H-gate, sil-
icon-on-insulator (SOI), T-gate.
electrical properties compared with bulk devices, especially for
high-speed and low-voltage/power applications . The most
option for next generation of ULSI circuits is that it provides
perfect isolation between individual device cells. However, for
partially depleted (PD) SOI devices, it has the floating body ef-
fects which are due to instability of body potential because of
the insulation between SOI layer and the silicon substrate by
buried oxide . In this letter, we use T-gate and H-gate struc-
tures (which is one side substrate contact and two sides sub-
strate contacts, respectively) to improve this drawback , .
Besides, to improve the current drive capability of MOSFETs at
low supply voltage (e.g.,
voltage applications. By shorting the gate to body, the threshold
voltage of the device is a function of its gate voltage, i.e., as
the gate voltage increases, the threshold voltage drops while the
device exhibits the normal threshold voltage in the off-state to
impacts of gate structure on SOI DTMOS have never been re-
ported in detail. Inthe present paper we report, for thefirst time,
the comparisons of SOI DTMOS with different substrate-con-
ILICON-ON-INSULATOR (SOI) devices are greatly com-
petitive for the ULSI era due to the significantly improved
V and below), the concep-
Manuscript received May 23, 2002. This work was supported by the National
Science Council of Taiwan, R.O.C. under Contract NSC-89-2215-E317-009.
The review of this letter was arranged by Editor B. Yu.
W.-C. Lo, S.-J. Chang, and C.-Y. Chang are with the Department of Elec-
tronic Engineering and Institute of Electronics, National Chiao-Tung Univer-
sity, Hsinchu, Taiwan, R.O.C.
T.-S. Chao is with the Department of Electrophysics, National Chiao-Tung
University, Hsinchu, Taiwan, R.O.C. and is also with the National Nano Device
Laboratories, Hsinchu, Taiwan, R.O.C. (e-mail: email@example.com).
Publisher Item Identifier 10.1109/LED.2002.801334.
Npoly-Si gate n-channel MOSFETs were fabricated using
-oriented separation by implanted oxygen
(SIMOX) wafers with top silicon thickness
140–190 nm. The buried oxide thickness was 400 nm. Local
oxidation of silicon (LOCOS) was performed to fully consume
the active silicon layer in the isolation region. Channel implant
was performed by BF
cleaning. Afterwards, a 200 nm poly-Si layer was deposited,
patterned, and etched to form the transistor gates. A shallow
S/D extension implant with As (5 keV,
was then performed, followed by the formation of a low
pressure CVD (LPCVD) TEOS spacer. Then, an As implant
at 10 keV with a dose of
form the n -doped source/drain regions. After the deposition
of passivation oxide and contact formation, wafers received
a rapid thermal annealing (RTA) at 1000 C for 10 s. Wafers
were then processed through a standard backend flow through
metallization. Finally, wafers were sintered at 400
30 min in forming gas.
cm ), followed by
cmwas performed to
III. RESULTS AND DISCUSSION
standard MOSFET mode changes to DTMOS mode of T-gate
and H-gate devices (as shown in the Fig. 1(a)). The channel
width are 100 m. The threshold voltage is measured at
mV at the intercept point on the
curve extrapolated from the point of maximum slope. Here
is the threshold voltage in MOSFET mode minus the
the H-gate structure device (empty circle) has larger threshold
voltagereduction thanT-gate(solid circle)counterpart.In order
to explain this phenomenon, we now consider DTMOS mode.
Since the gate is tied to body, namely, the body-to-source junc-
tion is “forward biased,” the equation of threshold voltage re-
axis of the versus
is body-effect factor and equal to
. From (1), at the same bias
reduction increases as the value of
device has lager value of
devices, respectively). This can explain why H-gate device has
a larger reduction of threshold voltage.
, the threshold voltage
increases. The H-gate
(for Si film thickness
are 0.376, and 0.286 for H- and T-gate
0741-3106/02$17.00 © 2002 IEEE
498IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 8, AUGUST 2002
??? ?m. (b) Reduction of ? operated in MOSFET mode changes to DTMOS
(a) Structures of T-gate (left) and H-gate (right) with channel width ?
MOSFET and DTMOS modes.
Drain current versus gate voltage for (a) H-gate (b) T-gate under
Fig. 2 shows the drain current versus gate voltage for H-gate
and T-gate under MOSFET mode (with different substrate
) and DTMOS mode. For both H-gate and T-gate, it is
quite obvious that devices under DTMOS mode operation can
get better subthreshold swing characteristics than conventional
MOSFET-mode operation. Besides, comparing H-gate with
T-gate devices, we can see that the H-gate devices show higher
saturation drain current than the T-gate ones. Regarding the
, saturation drain current, for long channel
One can get large saturation current if
cantly. As measured in Fig. 1, H-gate exhibits an increased ,
consequently, H-gate devices show increased drain current than
T-gate counterpart as shown in Fig. 2(a) and (b).
Fig. 3 shows the drain-induced barrier lowering, DIBL, of
T-gate and H-gate devices in MOSFET mode and DTMOS
is decreased signifi-
mode versus channel length.
DIBL of T-gate and H-gate devices in MOSFET mode and DTMOS
and DTMOS mode.
mode versus channel length. The devices have much lager
DIBL under MOSFET mode, especially for T-gate structure.
However, when devices are operated under DTMOS mode,
DIBL is dramatically reduced for both T-gate and H-gate
devices. Because DIBL is the change in the potential energy
barrier between the source and channel at the Si interface, it can
result from both the built-in p-n junction electric field and the
reverse-bias drain voltage. So, under DTMOS-mode operation,
provide a forward bias for body-to-source
and body-to-drain junction. This thus reduces the built-in
electric field of p-n junction and diminishes the effect of the
reverse-bias drain voltage. So DIBL is reduced significantly in
DTMOS mode. To treat the fair comparison of performances
between H-gate and T-gate devices, Fig. 4 shows the satu-
ration transconductance (Gm.sat) versus DIBL with T-gate
and H-gate devices in MOSFET mode and DTMOS mode.
For a given DIBL, H-gate DTMOS shows higher value of
saturation transconductance than T-gate NMOSFET. Besides,
the H-gate device operated under DTMOS-mode still has best
performance among these four operating modes.
The characteristics of SOI devices with different gate struc-
tures under MOSFET-mode and DTMOS-mode operation are
investigated. Since the gate is tied to body, the body-to-source
junction is “forward biased,” the threshold voltage of devices
willdecrease underDTMOS-mode operation.Thus, thedevices
can havehigher driving current, especiallyfor H-gate devices in
LO et al.: IMPACTS OF GATE STRUCTURE ON SOI nMOSFETs499
this study. Besides, for both T-gate and H-gate devices, DIBL
is drastically reduced operating in DTMOS-mode. To compare
devices performances, it is worth to note that the H-gate devices
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