An on-chip self-repair calculation and fusing methodology

IEEE Design and Test of Computers (Impact Factor: 1.62). 10/2003; DOI: 10.1109/MDT.2003.1232258
Source: DBLP

ABSTRACT Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

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    ABSTRACT: An approach is presented to create molecular electronics systems by introducing a multi-valued programmable logic (MVPL) block to model the characteristics recently observed experimentally in certain molecular structures to achieve circuit robustness on a molecular substrate. We show that— given the experimentally observed characteristics of certain types of molecular electronics substrates—we can adopt a multi-valued logic system for the logic blocks, thereby partially avoiding the need to incorporate specialized fault detection or fault tolerant circuitry at the molecular level that would be required in binary logic circuits.
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    ABSTRACT: A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed by the group compactor, the space compression circuit, and finally, the time compression circuit to reduce the volume of test response data. Both the space and time compression circuits implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock and by combining scan cells into groups of size r. When the size of constituent multiple-input signature register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2 lmB bits, where 1≤ B ≤ m. The experimental results show that the proposed diagnosis circuit that can locate up to four defective FRUs in the same test session can be implemented with less than one percent of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs.
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    ABSTRACT: Editor's note:As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.—Leland Chang, IBM T.J. Watson Research Center
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